US5157276A
Expired / Lapsed
US
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Low jitter clock phase adjust system
Assignee: Tektronix Inc
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Filing: 1991-09-26
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Granted: 1992-10-20
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Expires: 2011-09-26
Abstract
Abstract A low jitter clock phase adjust system divides an input clock signal into three clock signals having precisely equal phase differences from each other. The three clock signals are converted into current vectors and input to a trio of two-quadrature multipliers. The current vectors are multiplied by separate control signals generated from an input phase control signal. The separate control signals are generated such that only one of the separate control signals varies at a time. The result is a phase response output that is a linear function of the input phase control signal and that provides a phase adjustment range from -60° to 360°.
Inventors
- 👤 Arthur J. Metz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:51
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/62; H03K17/6257; H03K17/6264
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
92 words
A low jitter clock phase adjust system comprising: means for dividing an input sinewave signal into three sinewave signals equally spaced apart from each other in phase; means for multiplying each of the three sinewave signals by a separate control signal; means for generating the separate control signals in response to an input phase control signal such that only one of the separate control signals varies at a time; and means for summing the outputs of the multiplying means to produce a phase delayed sinewave signal corresponding to the input sinewave signal.
Claim 2
Dependent Claim
92 words
A low jitter clock phase adjust system comprising: means for dividing an input sinewave signal into three sinewave signals equally spaced apart from each other in phase; means for multiplying each of the three sinewave signals by a separate control signal; means for generating the separate control signals in response to an input phase control signal such that only one of the separate control signals varies at a time; and means for summing the outputs of the multiplying means to produce a phase delayed sinewave signal corresponding to the input sinewave signal.
Claim 3
Dependent Claim
75 words
A system as recited in claim 1 wherein the dividing means comprises at least two precision delay lines, each having as an input the input sinewave signal, to produce as two of the three sinewave signals a sinewave signal from one of the precision delay lines shifted one hundred twenty degrees output and a sinewave signal from the other of the precision delay lines shifted two hundred forty degrees output from the input sinewave signal.
Claim 4
Dependent Claim
29 words
A system as recited in claim 1 further comprising means for converting the three sinewave signals into three current vectors, the current vectors being input to the multiplying means.
Claim 5
Dependent Claim
38 words
A system as recited in claim 1 wherein the multiplying means comprises a trio of two-quadrature multipliers, each having as inputs a separate one of the three sinewave signals and the corresponding one of the separate control signals.
Claim 6
Dependent Claim
38 words
A system as recited in claim 1 wherein the multiplying means comprises a trio of two-quadrature multipliers, each having as inputs a unique pair of the three sinewave signals and the corresponding one of the separate control signals.
Claim 7
Dependent Claim
42 words
A system as recited in claim 1 wherein the generating means comprises a plurality of current switches coupled together and to the input phase control signal such that only one of the separate control signals varies while the other two remain constant.
Claim 8
Dependent Claim
47 words
A system as recited in claim 3 wherein the converting means comprises a trio of transistor emitter-coupled pairs, each pair having as inputs a unique pair of the three sinewave signals and producing as outputs corresponding pairs of the current vectors for input to the multiplying means.
Claim 9
Dependent Claim
70 words
A system as recited in claim 5 wherein each multiplier comprises a pair of emitter-coupled transistor pairs with the bases of the pair being cross-coupled and the bases of one pair being coupled to receive the separate control signal, the emitters of each pair being coupled to receive one of the unique pair of the three sinewave signals, and one collector of each pair being coupled to the summing means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-20 | 1996-04-20 | 1996-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-20 | 2000-04-20 | 2000-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-20 | 2004-04-20 | 2004-10-20 | $7700.00 | Window Closed / Lapsed |