US5148113A
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Clock phase alignment
Assignee: Ciena Luxembourg SARL
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Filing: 1990-11-29
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Granted: 1992-09-15
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Expires: 2010-11-29
Abstract
Abstract A phase error integrator for determining the phase error between a data signal and a clock signal frequency locked to the data signal has a data input and a clock input. In one embodiment the phase error integrator is formed as two functional components, namely a phase error detector and an integrator chain. The phase error detector sends to the integrator one of two output signals depending on whether the phase error is positive or negative. The integrator chain has a number of outputs the first half of which initially have a binary 1 and the second half of which initially have a binary 0. Depending on which output signal arrives from the phase error detector the binary 1's shift right or the binary 0's shift left. The integrator may be combined with a delay block connected to the outputs of the integrator chain. The data signal is fed to the delay block and delayed data output signal is obtained which is connected to the data input of the phase error integrator. The delay block delays the data signal until there is concordance between the phase of the clock and delayed data signals.
Inventors
- 👤 Mark S. Wight
- 👤 Valerie A. Van Alstine
- 👤 Gwendolyn K. Harris
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 07:17
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0337
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
154 words
A phase error integrator for determining the phase error between an NRZ data signal and a clock signal frequency locked to the data signal comprising a data input and a clock input, means for comparing the phase of said NRZ data signal applied to the data input with said clock signal applied to the clock input and deriving at N outputs a digital phase error output signal which at any point in time comprises a chain of N digits made up of M digits of a first binary sense (i.e. 1 or 0) followed by P digits of a second binary sense where M plus P equals N, the chain shifting the first binary sense digits right when the error between the data signal and the clock signal is in one sense (i.e. positive or negative) and the chain shifting the second binary sense digits left when the error is in the opposite sense.
Claim 2
Dependent Claim
154 words
A phase error integrator for determining the phase error between an NRZ data signal and a clock signal frequency locked to the data signal comprising a data input and a clock input, means for comparing the phase of said NRZ data signal applied to the data input with said clock signal applied to the clock input and deriving at N outputs a digital phase error output signal which at any point in time comprises a chain of N digits made up of M digits of a first binary sense (i.e. 1 or 0) followed by P digits of a second binary sense where M plus P equals N, the chain shifting the first binary sense digits right when the error between the data signal and the clock signal is in one sense (i.e. positive or negative) and the chain shifting the second binary sense digits left when the error is in the opposite sense.
Claim 3
Dependent Claim
94 words
A phase error integrator according to claim 1 in which the means for comparing is a phase error detector to which the data input and clock input are connected, the phase error detector providing one output signal when the phase error is in the one sense and another output signal when the phase error is in the opposite sense and the digital phase error output signal is derived at respective outputs of an integrating chain having N segments all of which are connected to receive the one output signal and the other output signal.
Claim 4
Dependent Claim
34 words
A phase error integrator according to claim 1 including a reset input to initialize the error output signal to M digits of the first binary sense and P digits of the second binary sense.
Claim 5
Dependent Claim
45 words
A phase error integrator according to claim 2 including a reset input connected both to the phase error detector and the integrating chain to initialize the error output signal to M digits of the first binary sense and P digits of the second binary sense.
Claim 6
Dependent Claim
50 words
A phase error integrator according to claim 4 in which the phase error detector comprises logic gates providing the one output signal at a first terminal and the other output signal at a second terminal, the first and second terminals being connected to respective input terminals of the integrating chain.
Claim 7
Dependent Claim
55 words
A phase error integrator according to claim 1 in which the means for comparing is functionally incorporated in a phase error integrating chain having N segments all of which are connected to the data and clock inputs, each segment having an output at which a respective digit of the digital phase error signal is obtained.
Claim 8
Dependent Claim
43 words
A phase error integrator according to claim 6 including a reset input connected to all the segments of the integrating chain to initialize the error output signal to M digits of the first binary sense and P digits of the second binary sense.
Claim 9
Dependent Claim
235 words
A phase alignment circuit for aligning a data signal with a clock signal to which it is frequency locked, comprising a phase error integrator and a delay block, the phase error integrator comprising a data input and a clock input, means for comparing the phase of said data signal applied to the data input with said clock signal applied to the clock input and deriving at N outputs a digital phase error output signal which at any point in time comprises a chain of N digits made up of M digits of a first binary sense (i.e. 1 or 0) followed by P digits of a second binary sense where M plus P equals N, the chain shifting the first binary sense digits right when the error between the data signal and the clock signal is in one sense (i.e. positive or negative) and the chain shifting the second binary sense digits left when the error is in the opposite sense, and the delay block having a plurality of inputs connected respectively to at least some of the N outputs of the phase error integrator, an input for receiving data and an output at which is provided a delayed data signal, the output being connected to the data input of the phase error integrator, the delay block delaying the data signal unit there is concordance between the phase of the clock and delayed data signals.
Claim 10
Dependent Claim
235 words
A phase alignment circuit for aligning a data signal with a clock signal to which it is frequency locked, comprising a phase error integrator and a delay block, the phase error integrator comprising a data input and a clock input, means for comparing the phase of said data signal applied to the data input with said clock signal applied to the clock input and deriving at N outputs a digital phase error output signal which at any point in time comprises a chain of N digits made up of M digits of a first binary sense (i.e. 1 or 0) followed by P digits of a second binary sense where M plus P equals N, the chain shifting the first binary sense digits right when the error between the data signal and the clock signal is in one sense (i.e. positive or negative) and the chain shifting the second binary sense digits left when the error is in the opposite sense, and the delay block having a plurality of inputs connected respectively to at least some of the N outputs of the phase error integrator, an input for receiving data and an output at which is provided a delayed data signal, the output being connected to the data input of the phase error integrator, the delay block delaying the data signal unit there is concordance between the phase of the clock and delayed data signals.
Claim 11
Dependent Claim
94 words
A phase alignment circuit according to claim 8 in which all of the N outputs of the phase error integrator except the first and last are connected to respective inputs of the delay block, the first and last outputs of the phase error integrator being connected to a circuit for determining overflow and underflow, said circuit for determining overflow and underflow being connected to a reset input of the phase error integrator to initialize the error output signal to M digits of the first binary sense and P digits of the second binary sense.
Claim 12
Dependent Claim
44 words
A phase alignment circuit according to claim 9 in which the phase error integrator provides a delayed data signal at an input which is connected to an input of a flip-flop to which the clock signal is fed whereby the data signal is reclocked.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-15 | 1996-03-16 | 1996-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-15 | 2000-03-16 | 2000-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-15 | 2004-03-16 | 2004-09-15 | $7700.00 | Window Closed / Lapsed |