US4878231A
Expired / Lapsed
US
⏱️ 0.0 years remaining
N-PI phase/frequency detector
Assignee: Gresham Worldwide Inc
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Filing: 1988-03-01
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Granted: 1989-10-31
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Expires: 2008-03-01
Abstract
Abstract A digital phase/frequency detector circuit in a phase locked loop comprises multiple bistable devices which are clocked up and down respectively by input and references digital signals to generate square waves. The duty ratio corresponds to the phase/frequency difference and sweeps repetitively between minimum and maximum values as the phase/frequency difference changes monotonically. The square waves are combined logically and additively in the output. The output is integrated to obtain an ever increasing output over many cycles of the phase/frequency difference until the maximum is reached depending on the number of bistable devices which are used. Added circuitry is used to avoid coincidence problems in the clocking input and reference digital signals, to minimize resultant irregularities, and hold the bistable devices at maximum or minimum, as appropriate, until the direction of phase/frequency difference reverses. At either maximum or minimum a sawtooth waveform exists of one magnitude of value out of many magnitudes of value between maximum and minimum. The many magnitudes depend on the number of bistable devices.
Inventors
- 👤 Steven P. Cok
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:34
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; G; G01; G01R; G01R25/00; G01R25/005
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
124 words
A digital phase/frequency detector circuit for detecting differences in phase and frequency between an input signal and a reference signal, comprising: means for receiving the input and reference signals; means for generating different value square wave signals having a duty ratio corresponding to a phase and frequency difference between said input and reference signals; means for adding together said square wave signals to provide a resultant square wave signal of unique values as said phase and frequency difference exceeds predetermined particular difference values; means for integrating said resultant square wave signal to provide a corresponding sawtooth wave signal which extends over plural sawtooth cycles; and means responsive to said sawtooth wave signal to provide an output signal representative of said phase and frequency difference.
Claim 2
Dependent Claim
124 words
A digital phase/frequency detector circuit for detecting differences in phase and frequency between an input signal and a reference signal, comprising: means for receiving the input and reference signals; means for generating different value square wave signals having a duty ratio corresponding to a phase and frequency difference between said input and reference signals; means for adding together said square wave signals to provide a resultant square wave signal of unique values as said phase and frequency difference exceeds predetermined particular difference values; means for integrating said resultant square wave signal to provide a corresponding sawtooth wave signal which extends over plural sawtooth cycles; and means responsive to said sawtooth wave signal to provide an output signal representative of said phase and frequency difference.
Claim 3
Dependent Claim
109 words
A digital phase/frequency detector circuit for detecting differences in phase and frequency between an input signal and a reference signal, comprising: means for receiving the input and reference signals; means for generating square waves having a duty ratio corresponding to a phase and frequency difference between said input and reference signals; means for integrating said square waves to provide corresponding sawtooth wave signals; means for adding together said sawtooth wave signals to provide a summed sawtooth wave signal when said phase and frequency difference exceeds a predetermined value; and means responsive to said summed sawtooth wave signal to provide an output signal representive of said phase and frequency difference.
Claim 4
Dependent Claim
109 words
A digital phase/frequency detector circuit for detecting differences in phase and frequency between an input signal and a reference signal, comprising: means for receiving the input and reference signals; means for generating square waves having a duty ratio corresponding to a phase and frequency difference between said input and reference signals; means for integrating said square waves to provide corresponding sawtooth wave signals; means for adding together said sawtooth wave signals to provide a summed sawtooth wave signal when said phase and frequency difference exceeds a predetermined value; and means responsive to said summed sawtooth wave signal to provide an output signal representive of said phase and frequency difference.
Claim 5
Dependent Claim
25 words
The circuit of claim 2, wherein said means for receiving includes first and second divider circuits receiving respectively said input signal and said reference signals.
Claim 6
Dependent Claim
31 words
The circuit of claim 2, wherein said means for integrating includes an up-down counter circuit and a digital-to-analog converter circuit responsive to said counter circuit for generating said sawtooth wave signals.
Claim 7
Dependent Claim
25 words
The circuit of claim 4, wherein said means to provide an output signal includes an amplifier circuit responsive to an output of said converter circuit.
Claim 8
Dependent Claim
26 words
The circuit of claim 5, including means for establishing an operating point of said amplifier circuit that is displaced from discontinuities of said sawtooth wave signals.
Claim 9
Dependent Claim
30 words
The circuit of claim 3, including correction circuitry for eliminating discontinuities of the output signal at phase and frequency differences between said input and reference signals of multiples of 2π.
Claim 10
Dependent Claim
89 words
The circuit of claim 7, wherein said correction circuitry includes coincidence detecting means for detecting coincidence between signal transitions at outputs of said first and second divider circuits, a time shifter circuit responsive to said coincidence detecting means for time shifting the signal at an output of one of said first and second divider circuits to cause the output signals of said first and second divider circuits to become non-coincident and make-up circuit means for generating compensating pulses corresponding to said output time shifting by said time shifter circuit.
Claim 11
Independent Claim
100 words
A method for detecting differences in phase and frequency between an input signal and a reference signal, comprising the steps of: receiving the input and reference signals; generating square waves having a duty ratio corresponding to a phase and frequency difference between said input and reference signals; integrating said square waves to provide corresponding sawtooth wave signals; adding together said sawtooth wave signals to provide a summed sawtooth wave signal when said phase and frequency difference exceeds a predetermined value; and responding to said summed sawtooth wave signal to provide an output signal representative of said phase and frequency difference.
Claim 12
Independent Claim
100 words
A method for detecting differences in phase and frequency between an input signal and a reference signal, comprising the steps of: receiving the input and reference signals; generating square waves having a duty ratio corresponding to a phase and frequency difference between said input and reference signals; integrating said square waves to provide corresponding sawtooth wave signals; adding together said sawtooth wave signals to provide a summed sawtooth wave signal when said phase and frequency difference exceeds a predetermined value; and responding to said summed sawtooth wave signal to provide an output signal representative of said phase and frequency difference.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-30 | 1993-05-01 | 1993-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-30 | 1997-05-01 | 1997-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-30 | 2001-05-01 | 2001-10-31 | $7700.00 | Window Closed / Lapsed |