US4535461A
Expired / Lapsed
US
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Digital clock bit synchronizer
Assignee: Cincinnati Electronics Corp
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Filing: 1983-06-01
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Granted: 1985-08-13
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Expires: 2003-06-01
Abstract
Abstract A clock wave is synchronized to the frequency of serial binary data bits. Digital circuitry derives a clock wave by responding to the data bits to selectively (a) increment a reference frequency, (b) decrement the reference frequency, and (c) not change the reference frequency. The digital circuitry divides each data bit into an even number of sub-bits. The binary value associated with a first half of the divided sub-bits of a particular data bit is compared with the binary value associated with a second half of the divided sub-bits of the particular data bit. In response to the derived clock wave and the comparison, the reference frequency is derived, incremented or decremented. The frequency of the source is respectively incremented and decremented in response to first and second relations of the binary value associated with the first half relative to the binary value associated with the second half. The frequency of the source is not changed when the binary values associated with the first and second halves are equal.
Inventors
- 👤 Elvin D. Stepp
- 👤 Gary L. Claypoole
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 17:01
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0331
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
232 words
Apparatus for synchronizing a clock wave normally having a reference frequency to the frequency of serial binary data bits comprising digital circuit means responsive to the data bits for deriving the clock wave by selectively (a) incrementing the reference frequency, (b) decrementing the reference frequency and (c) not changing the reference frequency, the digital circuit means including: means responsive to the derived clock wave for dividing each data bit into an even number of sub bits so that in each data bit there are (a) a first half of the divided sub bits and (b) the remaining sub bits of the data bit which comprises a second half of the divided sub bits, means for comparing the binary value associated with the first half of the divided sub bits of a particular data bit with the binary value associated with the remaining, second half of the divided sub bits of the particular data bit, and control means responsive to the derived clock wave and the comparing means for: (a) incrementing the reference frequency in response to a first relation between the relative binary values of the first and second halves, (b) decrementing the reference frequency in response to a second relation between the relative binary values of the first and second halves, and (c) not changing the feference frequency when the binary values associated with the first and second halves are equal.
Claim 2
Dependent Claim
232 words
Apparatus for synchronizing a clock wave normally having a reference frequency to the frequency of serial binary data bits comprising digital circuit means responsive to the data bits for deriving the clock wave by selectively (a) incrementing the reference frequency, (b) decrementing the reference frequency and (c) not changing the reference frequency, the digital circuit means including: means responsive to the derived clock wave for dividing each data bit into an even number of sub bits so that in each data bit there are (a) a first half of the divided sub bits and (b) the remaining sub bits of the data bit which comprises a second half of the divided sub bits, means for comparing the binary value associated with the first half of the divided sub bits of a particular data bit with the binary value associated with the remaining, second half of the divided sub bits of the particular data bit, and control means responsive to the derived clock wave and the comparing means for: (a) incrementing the reference frequency in response to a first relation between the relative binary values of the first and second halves, (b) decrementing the reference frequency in response to a second relation between the relative binary values of the first and second halves, and (c) not changing the feference frequency when the binary values associated with the first and second halves are equal.
Claim 3
Dependent Claim
112 words
The apparatus of claim 1 wherein the means for comparing includes a magnitude comparator for deriving first and second complementary output signals, the first and second signals respectively having first and second binary values in response to the binary value associated with the first half exceeding the binary value associated with the second half and having second and first values in response to the binary value associated with the second half exceeding the binary value associated with the first half, and first and second EXCLUSIVE OR gate means respectively responsive to the first and second signals and the data bits for deriving first and second output signals for controlling the control means.
Claim 4
Dependent Claim
97 words
The apparatus of claim 1 wherein the control means includes means for incrementing the reference frequency only in response to the number of data bits causing the reference frequency to be incremented exceeding the number of data bits causing the reference frequency to be decremented by a predetermined value in excess of one, and means for decrementing the reference frequency only in response to the number of data bits causing the reference frequency to be decremented exceeding the number of data bits causing the reference frequency to be incremented by a predetermined magnitude in excess of one.
Claim 5
Dependent Claim
19 words
The apparatus of claim 1 wherein the control means includes means for stepwise incrementing and decrementing the reference frequency.
Claim 6
Dependent Claim
43 words
The apparatus of claim 1 wherein the control means includes means for stepwise incrementing and decrementing the reference frequency for only one data bit period and for then deriving the clock wave at the reference frequency for at least one data bit period.
Claim 7
Dependent Claim
44 words
The apparatus of claim 1 wherein the control means includes means for preventing incrementing and decrementing of the reference frequency and for causing the frequency of the clock wave to be the reference frequency in response to successive data bits having the same value.
Claim 8
Dependent Claim
20 words
The apparatus of claim 6 wherein the control means includes means for only stepwise incrementing and decrementing the reference frequency.
Claim 9
Dependent Claim
43 words
The apparatus of claim 6 wherein the control means includes means for stepwise incrementing and decrementing the reference frequency for only one data bit period and for then deriving the clock wave at the reference frequency for at least one data bit period.
Claim 10
Dependent Claim
168 words
The apparatus of claim 1 wherein the means for comparing includes a magnitude comparator for deriving first and second complementary output signals and for deriving a third signal, the third signal having a first value in response to the binary value associated with the first half being equal to the binary value associated with the second half, means responsive to the data bit and the first and second signals for controlling incrementing and decrementing of the reference frequency, the first and second signals respectively having first and second binary values in response to the binary value associated with the first half exceeding the binary value associated with the second half and having second and first values in response to the binary value associated with the second half exceeding the binary value associated with the first half, and means responsive to the third signal having the first value for inhibiting incrementing and decrementing of the reference frequency and for causing the clock wave to be at the reference frequency.
Claim 11
Dependent Claim
37 words
The apparatus of claim 1 further including means for deriving a synchronizing signal when each data bit begins, and means responsive to the synchronizing signal for synchronizing the clock wave to the beginning of each data bit.
Claim 12
Dependent Claim
224 words
Apparatus for synchronizing a clock wave to the frequency of serial data bits comprising oscillator means for normally deriving 2N clock impulses during each data bit, an N bit accumulator register having a data input responsive to the serial data bits and clocked by the clock impulses, means responsive to the clock wave for deriving first and second signals respectively synchronized with the middle and end of each data bit, means for comparing the binary value of the N bits in the register when the first signal is derived with the binary value of the N bits in the register when the second signal is derived, the comparing means deriving indications of the relative binary values of the N bits in the register when the first and second signals are derived, means responsive to the indications and each of the data bits for controlling the frequency of the clock wave so the clock wave has: (a) a reference frequency when the means for comparing indicates the compared binary values are equal, (b) a frequency greater than the reference frequency when the means for comparing and each data bit indicates that the data bit lags the clock wave, and (c) a frequency less than the reference frequency when the means for comparing and each data bit indicates that the data bit leads the clock wave.
Claim 13
Dependent Claim
224 words
Apparatus for synchronizing a clock wave to the frequency of serial data bits comprising oscillator means for normally deriving 2N clock impulses during each data bit, an N bit accumulator register having a data input responsive to the serial data bits and clocked by the clock impulses, means responsive to the clock wave for deriving first and second signals respectively synchronized with the middle and end of each data bit, means for comparing the binary value of the N bits in the register when the first signal is derived with the binary value of the N bits in the register when the second signal is derived, the comparing means deriving indications of the relative binary values of the N bits in the register when the first and second signals are derived, means responsive to the indications and each of the data bits for controlling the frequency of the clock wave so the clock wave has: (a) a reference frequency when the means for comparing indicates the compared binary values are equal, (b) a frequency greater than the reference frequency when the means for comparing and each data bit indicates that the data bit lags the clock wave, and (c) a frequency less than the reference frequency when the means for comparing and each data bit indicates that the data bit leads the clock wave.
Claim 14
Dependent Claim
145 words
The apparatus of claim 11 wherein the comparing means includes means for deriving third and fourth signals, the third signal having a first value in response to the N bits in the register having a value when the first signal is derived that exceeds the value when the second signal is derived, the fourth signal having a first value in response to the N bits in the register having a value when the second signal is derived that exceeds the value when the first signal is derived, the clock wave controlling means including first and second EXCLUSIVE OR gate means respectively responsive to the third and fourth signals and the data bits for deriving first and second output signals for controlling the control means, the first and second output signals respectively causing the clock wave to have frequencies greater and less than the reference frequency.
Claim 15
Dependent Claim
97 words
The apparatus of claim 11 wherein the control means includes means for incrementing the reference frequency only in response to the number of data bits causing the reference frequency to be incremented exceeding the number of data bits causing the reference frequency to be decremented by a predetermined value in excess of one, and means for decrementing the reference frequency only in response to the number of data bits causing the reference frequency to be decremented exceeding the number of data bits causing the reference frequency to be incremented by a predetermined magnitude in excess of one.
Claim 16
Dependent Claim
19 words
The apparatus of claim 11 wherein the control means includes means for stepwise incrementing and decrementing the reference frequency.
Claim 17
Dependent Claim
43 words
The apparatus of claim 11 wherein the control means includes means for stepwise incrementing and decrementing the reference frequency for only one data bit period and for then deriving the clock wave at the reference frequency for at least one data bit period.
Claim 18
Dependent Claim
44 words
The apparatus of claim 11 wherein the control means includes means for preventing incrementing and decrementing of the reference frequency and for causing the frequency of the clock wave to be the reference frequency in response to successive data bits having the same value.
Claim 19
Dependent Claim
20 words
The apparatus of claim 16 wherein the control means includes means for only stepwise incrementing and decrementing the reference frequency.
Claim 20
Dependent Claim
43 words
The apparatus of claim 17 wherein the control means includes means for stepwise incrementing and decrementing the reference frequency for only one data bit period and for then deriving the clock wave at the reference frequency for at least one data bit period.
Claim 21
Dependent Claim
205 words
Apparatus for synchronizing a clock wave normally having a reference frequency to the frequency of serial binary data bits comprising digital circuit means responsive to the data bits for deriving the clock wave by selectively (a) incrementing the reference frequency, (b) decrementing the reference frequency and (c) not changing the reference frequency, the digital circuit means including: means responsive to the derived clock wave for dividing each data bit into nN sub bits so that each data bit is divided into n groups of N sub bits, means for comparing the binary values associated with the n groups of N sub bits with each other, and control means responsive to the derived clock wave and the comparing means for: (a) not changing the reference frequency when the binary values associated with the N bits of each of the n sub groups are the same, (b) incrementing the reference frequency when the binary values associated with the N bits of each of the n sub groups have a first relation different from being the same, and (c) decrementing the reference frequency when the binary values associated with the N bits of each of the n sub groups have a second relation different from being the same.
Claim 22
Dependent Claim
205 words
Apparatus for synchronizing a clock wave normally having a reference frequency to the frequency of serial binary data bits comprising digital circuit means responsive to the data bits for deriving the clock wave by selectively (a) incrementing the reference frequency, (b) decrementing the reference frequency and (c) not changing the reference frequency, the digital circuit means including: means responsive to the derived clock wave for dividing each data bit into nN sub bits so that each data bit is divided into n groups of N sub bits, means for comparing the binary values associated with the n groups of N sub bits with each other, and control means responsive to the derived clock wave and the comparing means for: (a) not changing the reference frequency when the binary values associated with the N bits of each of the n sub groups are the same, (b) incrementing the reference frequency when the binary values associated with the N bits of each of the n sub groups have a first relation different from being the same, and (c) decrementing the reference frequency when the binary values associated with the N bits of each of the n sub groups have a second relation different from being the same.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-08-12 | 1989-02-11 | 1989-08-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-08-12 | 1993-02-11 | 1993-08-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-08-12 | 1997-02-11 | 1997-08-13 | $7700.00 | Window Closed / Lapsed |