Frequency modulation in a phase-locked loop

Claim 2

An electronic apparatus for frequency modulation of a multiplicity of frequencies which are desired rational multiples of a reference frequency generated in a phase-locked loop, said apparatus comprising: frequency generating means for producing an output signal with a frequency responsive to the level of a control input signal; first counting means responsive to the output of the frequency generating means for producing an output signal with a frequency equal to the frequency of a signal at the input of the first counting means divided by N; phase comparison means coupled to the first counting means for comparing the phases of the output signal from the first counting means and a reference signal and generating an error signal indicative of a phase difference therebetween, said error signal serving as the control input signal to the frequency generating means to thereby vary the frequency of the output signal from the frequency generating means; integrating means coupled to the output of the phase comparison means for integrating a frequency modulation input signal and producing an output signal which is summed with said error signal thereby phase modulating the output signal from the frequency generating means; input means for summing said frequency modulation signal with the control input signal for producing frequency modulation of the output signal from the frequency generating means; first comparator means coupled to the output of the integrating means for comparing the output of the integrating means to a predetermined arbitrary first voltage level for producing a high threshold pulse whenever the output of the integrating means exceeds said first voltage level; second comparator means coupled to the output of the integrating means for comparing the output of the integrating means to a predetermined arbitrary second voltage level, said first voltage level greater than said second voltage level, for producing a low threshold pulse whenever the output of the integrating means is less than said second voltage level; cycle removal means interconnected between the frequency generating means and the first counting means, said cycle removal means responsive to the high threshold pulse to remove at least one cycle from the input of the first counting means thereby removing a multiple of two pi radians of accumulated phase shift from the input signal to the first counting means; cycle addition means interconnected between the frequency generating means and the first counting means, said cycle addition means responsive to the low threshold pulse to add at least one cycle to the input of the first counting means for adding a multiple of two pi radians of accumulated phase shift to the input signal to the counting means; first current generating means coupled to the input of the integrating means responsive to the high threshold pulse for inputting a reset current into the integrating means input to reset the output of the integrating means a predetermined amount below said predetermined first voltage level, said predetermined amount cancelling exactly said multiple of two pi radians of phase shift removed from the input signal to the first counting means; and second current generating means coupled to the input of the integrating means responsive to the low threshold pulse for inputting a reset current into the integrating means input to reset the output of the integrating means a predetermined amount above said predetermined second voltage level, said predetermined amount cancelling exactly said multiple of two pi radians of phase shift added to the input signal to the first counting means.

Claim 3

Apparatus as in claim 1 further comprising a loop filter means interconnected between the output of the phase comparison means and the input of the frequency generating means for removing undesirable components from said error signal.

Claim 4

Apparatus as in claim 2 wherein said cycle removal means and said cycle addition means comprise a three-modulus prescaler.

Claim 5

Apparatus as in claim 3 wherein said prescaler comprises a six-bit ring counter coupled to a divide-by-two flip-flop.

Claim 6

An electronic apparatus for frequency modulation of a multiplicity of frequencies which are desired rational multiples of a reference frequency generated in a phase-locked loop, said apparatus comprising: frequency generating means for producing an output signal with frequency responsive to the level of a control input signal; first counting means responsive to the output of the frequency generating means for producing an output signal with a frequency equal to the frequency of a signal at the input of the first counting means divided by a predetermined divisor N; phase comparison means coupled to the first counting means for comparing the phases of the output signal from the first counting means and the reference signal and generating an error signal indicative of a phase difference therebetween, said error signal serving as the control input signal to the frequency generating means to thereby vary the frequency of the output signal from the frequency generating means; integrating means coupled to the output of the phase comparison means for integrating a frequency modulation input signal and producing an output signal which is summed with said error signal thereby phase modulating the output signal from the frequency generating means; input means for summing said frequency modulation signal with the control input signal for producing frequency modulation of the output signal from the frequency generating means; first comparator means coupled to the output of the integrating means for comparing the output of the integrating means to a predetermined arbitrary first voltage level for producing a high threshold pulse whenever the output of the integrating means exceeds said first voltage level; second comparator means coupled to the output of the integrating means for comparing the output of the integrating means to a predetermined arbitrary second voltage level, said first voltage level greater than said second voltage level for producing a low threshold pulse whenever the output of the integrating means is less than said second voltage level; cycle removal means interconnected between the frequency generating means and the first counting means, said cycle removal means responsive to the high threshold pulse to remove at least one cycle from the input of the first counting means thereby removing a multiple of two pi radians of accumulated phase shift from the input signal to the first counting means; cycle addition means interconnected between the frequency generating means and the first counting means, said cycle addition means responsive to the low threshold pulse to add at least one cycle to the input of the first counting means for adding a multiple of two pi radians of accumulated phase shift to the input signal to the counting means; first current generating means coupled to the input of the integrating means responsive to the high threshold pulse for inputting a reset current into the integrating means input to reset the output of the integrating means a predetermined amount below said predetermined first voltage level, said predetermined amount cancelling exactly said multiple of two pi radians of phase shift removed from the input signal to the first counting means; and second current generating means coupled to the input of the integrating means responsive to the low threshold pulse for inputting a reset current into the integrating means input to reset the output of the integrating means a predetermined amount above said predetermined second voltage level, said predetermined amount cancelling exactly said multiple of two pi radians of phase shift added to the input signal to the first counting means; second counting means responsive to the high threshold pulses and the low threshold pulses for producing a digital signal indicative of the net number of cycles added to and removed from the input to the first counting means; digital-to-analog converter means coupled to the second counting means and responsive to said digital signal for producing a voltage signal proportional to the net number of cycles removed from and added to the input of the first counting means; resistive feedback means coupled to the output of the integrating means and the output of the digital-to-analog converter means and to the input of the integrating means, said resistive feedback means responsive to the output of the integrating means and the output of the digital-to-analog means for producing a feedback current to the input of the integrating means, said feedback current proportional to the amount of phase that the output of the frequency generating means is away from the center frequency of the output of the frequency generating means; and switching means disposed between the resistive feedback means and the input of the integrating means for interrupting said feedback current path.

Claim 7

An electronic apparatus for frequency modulation of a multiplicity of frequencies which are desired rational multiples of a reference frequency generated in a phase-locked loop, said apparatus comprising: frequency generating means for producing an output signal with frequency responsive to the level of a control input signal; first counting means responsive to the output of the frequency generating means for producing an output signal with a frequency equal to the frequency of a signal at the input of the first counting means divided by a predetermined divisor N; phase comparison means coupled to the first counting means for comparing the phases of the output signal from the first counting means and the reference signal and generating an error signal indicative of a phase difference therebetween, said error signal serving as the control input signal to the frequency generating means to thereby vary the frequency of the output signal from the frequency generating means; integrating means coupled to the output of the phase comparison means for integrating a frequency modulation input signal and producing an output signal which is summed with said error signal thereby phase modulating the output signal from the frequency generating means; input means for summing said frequency modulation signal with the control input signal for producing frequency modulation of the output signal from the frequency generating means; first comparator means coupled to the output of the integrating means for comparing the output of the integrating means to a predetermined arbitrary first voltage level for producing a high threshold pulse whenever the output of the integrating means exceeds said first voltage level; second comparator means coupled to the output of the integrating means for comparing the output of the integrating means to a predetermined arbitrary second voltage level, said first voltage level greater than said second voltage level for producing a low threshold pulse whenever the output of the integrating means is less than said second voltage level; cycle removal means interconnected between the frequency generating means and the first counting means, said cycle removal means responsive to the high threshold pulse to remove at least one cycle from the input of the first counting means thereby removing a multiple of two pi radians of accumulated phase shift from the input signal to the first counting means; cycle addition means interconnected between the frequency generating means and the first counting means, said cycle addition means responsive to the low threshold pulse to add at least one cycle to the input of the first counting means for adding a multiple of two pi radians of accumulated phase shift to the input signal to the counting means; first current generating means coupled to the input of the integrating means responsive to the high threshold pulse for inputting a reset current into the integrating means input to reset the output of the integrating means a predetermined amount below said predetermined first voltage level, said predetermined amount cancelling exactly said multiple of two pi radians of phase shift removed from the input signal to the first counting means; and second current generating means coupled to the input of the integrating means responsive to the low threshold pulse for inputting a reset current into the integrating means input to reset the output of the integrating means a predetermined amount above said predetermined second voltage level, said predetermined amount cancelling exactly said multiple of two pi radians of phase shift added to the input signal to the first counting means; second counting means responsive to the high threshold pulses and the low threshold pulses for producing a digital signal indicative of the net number of cycles added to and removed from the input to the first counting means; digital-to-analog converter means coupled to the second counting means and responsive to said digital signal for producing a voltage signal proportional to the net number of cycles removed from and added to the input of the first counting means; resistive feedback means coupled to the output of the integrating means and the output of the digital-to-analog converter means and to the input of the integrating means, said resistive feedback means responsive to the output of the integrating means and the output of the digital-to-analog means for producing a feedback current to the input of the integrating means, said feedback current proportional to the amount of phase that the output of the frequency generating means is away from the center frequency of the output of the frequency generating means; and switching means disposed between the resistive feedback means and the input of the integrating means for interrupting said feedback current path.

Claim 8

Apparatus as in claim 5 further comprising a loop filter means interconnected between the output of the phase comparison means and the input of the frequency generating means for removing undesirable components from said error signal.

Claim 9

Apparatus as in claim 6 wherein said cycle removal means and said cycle additional means comprise a three-modulus prescaler.

Claim 10

Apparatus as in claim 7 wherein said prescaler comprises a six-bit ring counter coupled to a divide-by-two flip-flop.

Claim 11

Apparatus as in claim 6 wherein said second counting means comprises an up/down counter.