Phase detector circuit having latched output characteristic

Claim 2

A phase detector circuit operative in response to first and second input signals having a phase relationship, comprising: means for generating a signal indicative of said phase relationship between the first and second input signals; means for detecting when said phase relationship between the first and second input signals is outside a predetermined desired range; and means responsive to the detecting means for decoupling said first and second signals from said generating means when said phase relationship is outside the predetermined desired range.

Claim 3

A phase detector circuit operative in response to first and second input signals comprising means for generating a signal indicative of the phase relationship between the first and second input signals as described in claim 1 wherein said first input signal is a reference signal and said second input signal is a signal of variable frequency.

Claim 4

A phase detector circuit operative in response to first and second input signals comprising means for generating a signal indicative of the phase relationship between the first and second input signals as described in claim 2 wherein said generating means comprises a differential phase detector.

Claim 5

A phase detector circuit operative in response to first and second input signals comprising means for generating a signal indicative of the phase relationship between the first and second input signals as described in claim 3 wherein said detecting means comprises proportional phase detector means.

Claim 6

A phase detector circuit operative in response to first and second input signals comprising means for generating a signal indicative of the phase relationship between the first and second input signals as described in claim 4 wherein said proportional phase detector means comprises: a first proportional phase detector for detecting a phase relationship between said first and second input signals that is greater in magnitude than said predetermined desired range; and a second proportional phase detector for detecting a phase relationship between said first and second input signals that is lesser in magnitude than said predetermined desired range.

Claim 7

A phase detector for producing an error signal indicative of the phase relationship between a clock signal R and a variable frequency signal V, comprising: a differential phase detector having first and second inputs and providing first and second output signals which constitute an error signal indicative of the phase relationship between said R signal and V signal; a first AND gate having its output coupled to the first input of the differential phase detector and the R signal coupled to a first input thereof; a second AND gate having its output coupled to the second input of the differential phase detector and the V signal coupled to a first input thereof; a first DC flip flop having its output coupled to a second input of the first AND gate and having the C input thereof coupled to said V signal; a second DC flip flop having its output coupled to a second input of the second AND gate and having the C input thereof coupled to said R signal; a first proportional phase detector having its output coupled to the D input of the first DC flip flop and its inputs coupled to said R and V signals; and a second proportional phase detector having its output coupled to the D input of the second D-C flip flop and its inputs coupled to said R and V signals.

Claim 8

A phase detector for producing an error signal indicative of the phase relationship between a clock signal R and a variable frequency signal V, comprising: a differential phase detector having first and second inputs and providing first and second output signals which constitute an error signal indicative of the phase relationship between said R signal and V signal; a first AND gate having its output coupled to the first input of the differential phase detector and the R signal coupled to a first input thereof; a second AND gate having its output coupled to the second input of the differential phase detector and the V signal coupled to a first input thereof; a first DC flip flop having its output coupled to a second input of the first AND gate and having the C input thereof coupled to said V signal; a second DC flip flop having its output coupled to a second input of the second AND gate and having the C input thereof coupled to said R signal; a first proportional phase detector having its output coupled to the D input of the first DC flip flop and its inputs coupled to said R and V signals; and a second proportional phase detector having its output coupled to the D input of the second D-C flip flop and its inputs coupled to said R and V signals.

Claim 9

A phase detector for producing an error signal indicative of the phase relationship between a clock signal R and a variable frequency signal V as described in claim 6 further including an integrator coupled to said first and second outputs of said differential phase detector.