Circuit providing improved lock-in for a phase-locked loop

Claim 2

A circuit for generating a signal indicative of the phase relationship between a signal R and a signal V comprising: first phase detector means having a desired operation range of phase relationship between signal R and V; means for gating signals R and V to the first phase detector means; and means for disabling the gating means when the phase relationship between signals R and V is outside the desired operation range.

Claim 3

A circuit for generating a signal indicative of the phase relationship between a signal R and a signal V as described in claim 1 wherein said disabling means comprises a second phase detector means.

Claim 4

A circuit for generating a signal indicative of the phase relationship between a signal R and a signal V as described in claim 2 wherein said first phase detector means comprises a differential phase detector for producing phase outputs Q R and Q V .

Claim 5

A circuit for generating a signal indicative of the phase relationship between a signal R and a signal V as described in claim 3 wherein said second phase detector means comprises a proportional phase detector.

Claim 6

A circuit for generating a signal indicative of the phase relationship between a signal R and a signal V as described in claim 4 wherein said gating means comprises an AND-gate.

Claim 7

A circuit for generating a signal indicative of the phase relationship between a signal R and a signal V as described in claim 4 further including means for combining said Q R and Q V outputs from said differential phase detector.

Claim 8

A circuit for generating a signal indicative of the phase relationship between a signal R and a signal V as described in claim 6 further including means for integrating the output from said combining means.

Claim 9

A phase-locked-loop, comprising: a voltage controlled oscillator; feedback means coupled to the output of the voltage controlled oscillator and providing a variable signal V related to the output signal from said voltage controlled oscillator; a reference signal source producing an R signal; a low pass filter coupled to said voltage controlled oscillator; an integrator coupled to the low pass filter; a differential phase detector having its output coupled to said integrator; means for detecting a phase relationship between said R and V signals outside a predetermined range, said detecting means having its input coupled to the R and V signals and its output coupled to said integrator; and means in said detecting means for decoupling said R and V signals from the proportional phase detector in response to said detecting means.

Claim 10

A phase-locked-loop, comprising: a voltage controlled oscillator; feedback means coupled to the output of the voltage controlled oscillator and providing a variable signal V related to the output signal from said voltage controlled oscillator; a reference signal source producing an R signal; a low pass filter coupled to said voltage controlled oscillator; an integrator coupled to the low pass filter; a differential phase detector having its output coupled to said integrator; means for detecting a phase relationship between said R and V signals outside a predetermined range, said detecting means having its input coupled to the R and V signals and its output coupled to said integrator; and means in said detecting means for decoupling said R and V signals from the proportional phase detector in response to said detecting means.

Claim 11

A phase lock loop as described in claim 8 wherein said feedback means comprises a divider.

Claim 12

A phase lock loop as described in claim 8 wherein said detecting means comprises a proportional phase detector.

Claim 13

A phase lock loop as described in claim 9 wherein said detecting means further comprises a second proportional phase detector.