US4635000A
Expired / Lapsed
US
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Temporal pixel clock synchronization system
Assignee: Xerox Corp
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Filing: 1985-11-12
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Granted: 1987-01-06
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Expires: 2005-11-12
Abstract
Abstract A temporal pixel clock synchronization system with jitter correction for an optical scanning system having a continuously running pixel clock source, circuitry for generating timing error signals having an amplitude representing any phase error between start of scan and start of pixel count pulses and any phase error between end of scan and end of pixel count pulses and circuitry, including a switched filter circuit with two storage elements for each facet of the polygon of the system, for generating a frequency correction signal for the pixel clock source.
Inventors
- 👤 Melvin E. Swanberg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 14:05
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/089; H03L7/10; H03L7/107; H03L7/1075; H04; H04N; H04N1/00; H04N1/04; H04N1/047; H04N1/053; H04N1/113; H04N1/1135; H04N2201/00; H04N2201/024; H04N2201/02406; H04N2201/02439; H04N2201/04; H04N2201/047; H04N2201/04701; H04N2201/0471; H04N2201/04732; H04N2201/04744; H04N2201/04753; H04N2201/04758; H04N2201/04767; H04N2201/04768; H04N2201/04772; H04N2201/04777; H04N2201/04781; H04N2201/04786; H04N2201/04793; H04N2201/04794
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
187 words
A temporal pixel clock synchronization system with jitter correction for an optical line scanner system having a polygon scanner, including first means for generating both a start of scan pulse and an end of scan pulse, second means for generating both a start of pixel count pulse and an end of pixel count pulse, third means coupled to said first and second means and supplied with said pulses for generating a timing error signal having an amplitude representing any error between the phase of the start of scan pulse and the start of count pulse and any error between the phase of the end of scan pulse and the end of count pulse, fourth means for generating a continuous oscillatory signal, fifth means coupled to the output of said third means and to the input of said fourth means and including a switched filter circuit with two storage elements for each facet of said polygon for generating from said error signal a frequency correction signal for said fourth means, and sixth means for coupling the output of said fourth means to the input of said second means.
Claim 2
Dependent Claim
187 words
A temporal pixel clock synchronization system with jitter correction for an optical line scanner system having a polygon scanner, including first means for generating both a start of scan pulse and an end of scan pulse, second means for generating both a start of pixel count pulse and an end of pixel count pulse, third means coupled to said first and second means and supplied with said pulses for generating a timing error signal having an amplitude representing any error between the phase of the start of scan pulse and the start of count pulse and any error between the phase of the end of scan pulse and the end of count pulse, fourth means for generating a continuous oscillatory signal, fifth means coupled to the output of said third means and to the input of said fourth means and including a switched filter circuit with two storage elements for each facet of said polygon for generating from said error signal a frequency correction signal for said fourth means, and sixth means for coupling the output of said fourth means to the input of said second means.
Claim 3
Dependent Claim
39 words
The pixel clock system of claim 1 wherein said fifth means further includes a band pass filter coupled directly to the output of said third means, said switched filter circuit connected to receive the output of said bandpass filter.
Claim 4
Dependent Claim
18 words
The pixel clock system of claim 3 wherein said third means includes a phase comparator and an integrator.
Claim 5
Dependent Claim
18 words
The pixel clock system of claim 1 wherein said fourth means is a continuously running voltage controlled oscillator.
References Cited (Backward Citations)
US4320420A
Cited
US4342050A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-05 | 1990-07-07 | 1991-01-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-05 | 1994-07-07 | 1995-01-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-05 | 1998-07-07 | 1999-01-06 | $7700.00 | Window Closed / Lapsed |