Low threshold BiCMOS circuit

Claim 1

An improved BiCMOS logic circuit providing full rail-to-rail output voltage and high-speed operation comprising: a conventional CMOS NAND input stage; a push-pull output stage comprised of a series-connected pair of bipolar transistors driven by the CMOS NAND stage output; a series-connected pair of low threshold n-channel field effect transistors, which improve the output falling delay, connected between the base and collector terminals of the pull-down transistor of the bipolar push-pull output stage; a series-connected pair of standard threshold n-channel field effect transistors connected between the output and ground driven by the input signals; a p-channel field effect transistor connected between the output and a power supply, said p-channel FET driven by a standard CMOS inverter circuit which is connected to the output; and a low threshold n-channel field effect transistor with grounded gate and source terminals and drain terminal connected to the base terminal of the pull-down transistor of the bipolar push-pull output stage used as a bleed transistor.