BiCMOS logic circuits with reduced crowbar current

Claim 2

A BiCMOS integrated logic circuit, comprising: a pair of bipolar transistors connected in totem-pole fashion to provide an emitter-collector output connection; a pair of complementary MOS field-effect transistors connected in push-pull fashion for each receiving a common input signal on a gate thereof and for driving a base of a corresponding one of the bipolar transistors; and resistor means connected to the field-effect transistors for isolating the output connection and substantially eliminating crowbar current.

Claim 3

A BiCMOS integrated logic circuit according to claim 1 wherein the bipolar transistors are both of the NPN type and an emitter of a first one of the bipolar transistors is connected to a collector of a second one of the bipolar transistors to form the emitter-collector output connection and an emitter of the second bipolar transistor is connected to a ground.

Claim 4

A BiCMOS integrated logic circuit according to claim 2 wherein a first one of the field-effect transistors is a p-channel MOSFET having a drain connected to a drain of a second one of the field-effect transistors which is an n-channel MOSFET.

Claim 5

A BiCMOS integrated logic circuit according to claim 3 wherein a source of the p-channel MOSFET is connected to a voltage source and a collector of the first bipolar transistor.

Claim 6

A BiCMOS integrated logic circuit according to claim 4 wherein the drain of the p-channel MOSFET is connected to a base of the first bipolar transistor.

Claim 7

A BiCMOS integrated logic circuit according to claim 5 wherein a source of the n-channel MOSFET is connected to a base of the second bipolar transistor.

Claim 8

A BiCMOS integrated logic circuit according to claim 6 wherein the resistor means includes a first resistor which connects the drain of the p-channel MOSFET to the drain of the n-channel MOSFET.

Claim 9

A BiCMOS integrated logic circuit according to claim 7 and further comprising a second resistor which connects the source of the n-channel MOSFET to the ground.

Claim 10

A BiCMOS integrated logic circuit according to claim 8 wherein the resistor means further includes a third resistor which connects the drain of the n-channel MOSFET to the emitter-collector output connection.

Claim 11

A BiCMOS integrated logic circuit according to claim 9 wherein a resistance value of the third resistor is sufficiently large relative to a resistance value of the first resistor to allow the first bipolar transistor to turn ON rapidly while also allowing the n-channel MOSFET to discharge a signal at the base of the first bipolar transistor before the second bipolar transistor turns ON to thereby substantially reduce crowbar current.

Claim 12

A BiCMOS integrated logic circuit according to claim 1 wherein the sum of the resistance values of the first and third resistors is substantially equal to a resistance value of the second resistor.

Claim 13

A BiCMOS integrated circuit, comprising: a p-channel MOSFET; an n-channel MOSFET; a gate of the p-channel MOSFET being connected to a gate of the n-channel MOSFET; a first resistor connecting a drain of the p-channel MOSFET to a drain of the n-channel MOSFET; a second resistor connecting a source of the n-channel MOSFET to a ground; a first NPN bipolar transistor having a base connected to the drain of the p-channel MOSFET and a collector connected to a drain of the p-channel MOSFET; a second NPN bipolar transistor having a base connected to the source of the n-channel MOSFET, a collector connected to an emitter of the first NPN bipolar transistor, and an emitter connected to the ground; a third resistor connecting the drain of the n-channel MOSFET to the emitter of the first NPN bipolar transistor and the collector of the second NPN bipolar transistor; and a resistance value of the third resistor being sufficiently large relative to a resistance value of the first resistor to allow the first NPN bipolar transistor to turn ON rapidly while also allowing the n-channel MOSFET to discharge a signal at the base of the first NPN bipolar transistor before the second NPN bipolar transistor turns ON to thereby substantially reduce crowbar current.

Claim 14

A BiCMOS integrated circuit, comprising: a p-channel MOSFET; an n-channel MOSFET; a gate of the p-channel MOSFET being connected to a gate of the n-channel MOSFET; a first resistor connecting a drain of the p-channel MOSFET to a drain of the n-channel MOSFET; a second resistor connecting a source of the n-channel MOSFET to a ground; a first NPN bipolar transistor having a base connected to the drain of the p-channel MOSFET and a collector connected to a drain of the p-channel MOSFET; a second NPN bipolar transistor having a base connected to the source of the n-channel MOSFET, a collector connected to an emitter of the first NPN bipolar transistor, and an emitter connected to the ground; a third resistor connecting the drain of the n-channel MOSFET to the emitter of the first NPN bipolar transistor and the collector of the second NPN bipolar transistor; and a resistance value of the third resistor being sufficiently large relative to a resistance value of the first resistor to allow the first NPN bipolar transistor to turn ON rapidly while also allowing the n-channel MOSFET to discharge a signal at the base of the first NPN bipolar transistor before the second NPN bipolar transistor turns ON to thereby substantially reduce crowbar current.

Claim 15

A BiCMOS integrated logic circuit according to claim 12 wherein the sum of the resistance values of the first and third resistors is substantially equal to a resistance value of the second resistor.

Claim 16

A BiCMOS integrated logic circuit according to claim 12 wherein the resistance value of the first resistor is approximately one-third the resistance value of the third resistor.

Claim 17

A BiCMOS integrated logic circuit according to claim 12 and further comprising a plurality of p-channel MOSFETs connected in parallel and a plurality of n-channel MOSFETs connected in series to thereby configure the circuit in the form of an NAND gate.