US4733110A
Expired / Lapsed
US
⏱️ 0.0 years remaining
BICMOS logical circuits
Assignee: Toshiba Corp
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Filing: 1987-03-23
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Granted: 1988-03-22
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Expires: 2007-03-23
Abstract
Abstract Logical NAND circuits, each consisting of a logical operational portion, an output control portion comprising the combination of a bipolar transistor and a plurality of NMOS transistors, and an output portion comprising first and second bipolar transistors connected in series between power supply voltage and the ground in which the merits of the MOS transistors and the bipolar transistors can be demonstrated by the particular combination of the two different kinds of the transistors in the logical circuit, thereby increasing the current driving performance while reducing power consumption without making the size of the logical circuit large.
Inventors
- 👤 Hiroyuki Hara
- 👤 Yasuhiro Sugimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:11
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/094; H03K19/0944; H03K19/09448
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
263 words
A logical circuit which comprises: a logical operational portion (21) consisting of first and second type MOS transistors for performing a logical operation of input signals; an output control portion (25) having an inverter circuit (41) for inverting an output signal from said operational portion and the remaining circuit portion comprising a first bipolar transistor (43) connected between power supply (V DD ) and the ground and conductively controlled by the output signal from said inverter circuit, a first-type first MOS transistor (55) conductively controlled by the output signal from said logical operational portion, a first-type second MOS transistor (47) connected between an output terminal and the ground and conductively controlled by the emitter potential of said bipolar transistor, a first-type third MOS transistor (49) conductively controlled by the output signal from said inverter circuit and a first-type fourth MOS transistor (51) conductively controlled by the output signal from said logical operational portion, said first-type third and fourth MOS transistors being connected in series between the output terminal and the ground; and an output portion (23) consisting of a second bipolar transistor (37) conductively controlled by the output signal from said logical operational portion and a third bipolar transistor (39) conductively controlled by the output signal from the source potential of the first-type third MOS transistor, said second and third bipolar transistors being connected in series between the power supply and the ground for producing the result of the logical operation of the input signals with the junction of the series connected bipolar transistors being the output terminal (OUT) of the logical circuit.
Claim 2
Dependent Claim
263 words
A logical circuit which comprises: a logical operational portion (21) consisting of first and second type MOS transistors for performing a logical operation of input signals; an output control portion (25) having an inverter circuit (41) for inverting an output signal from said operational portion and the remaining circuit portion comprising a first bipolar transistor (43) connected between power supply (V DD ) and the ground and conductively controlled by the output signal from said inverter circuit, a first-type first MOS transistor (55) conductively controlled by the output signal from said logical operational portion, a first-type second MOS transistor (47) connected between an output terminal and the ground and conductively controlled by the emitter potential of said bipolar transistor, a first-type third MOS transistor (49) conductively controlled by the output signal from said inverter circuit and a first-type fourth MOS transistor (51) conductively controlled by the output signal from said logical operational portion, said first-type third and fourth MOS transistors being connected in series between the output terminal and the ground; and an output portion (23) consisting of a second bipolar transistor (37) conductively controlled by the output signal from said logical operational portion and a third bipolar transistor (39) conductively controlled by the output signal from the source potential of the first-type third MOS transistor, said second and third bipolar transistors being connected in series between the power supply and the ground for producing the result of the logical operation of the input signals with the junction of the series connected bipolar transistors being the output terminal (OUT) of the logical circuit.
Claim 3
Dependent Claim
16 words
The logical circuit as claimed in claim 1 wherein the logical circuit is a NAND circuit.
Claim 4
Dependent Claim
90 words
The logical circuit as claimed in claim 1 wherein the first and second-type MOS transistors in the logical operational portion are PMOS and NMOS transistors, each gate electrode of which being connected to each of the input terminals and each of the source electrodes of the PMOS transistors is connected to the power supply, while each of the source electrodes of the NMOS transistors is connected in series to each other and each drain of the PMOS transistors is connected as a common output terminal of the logical operational portion.
Claim 5
Dependent Claim
22 words
The logical circuit as claimed in claim 1 wherein said first-type first, second third, and fourth MOS transistors are NMOS transistors, respectively.
Claim 6
Dependent Claim
259 words
A logical circuit which comprises: a logical operation portion (21) consisting of first and second-type MOS transistors for performing a logical operation of input signals; an output control portion (25) having an inverter circuit portion (41) for inverting an output signal from said operational portion and the remaining circuit portion comprising a first bipolar transistor (43') connected between power supply (V DD ) and the ground and conductively controlled by the output signal from said logical operation portion, a first-type first MOS transistor (45') conductively controlled by the output signal from said inverter circuit, a first-type second MOS transistor (47') connected between an output terminal and the ground and conductively controlled by the emitter potential of said first bipolar transistor, a first-type third MOS transistor (51') conductively controlled by the output signal from said inverter circuit and a first-type fourth MOS transistor (49') conductively controlled by the output signal from said logical operational portion, said first-type third and fourth MOS transistors being connected in series between the output terminal and the ground; and an output portion (23) consisting of a second bipolar transistor (37) conductively controlled by the output signal from said inverter circuit and a third bipolar transistor (39) conductively controlled by the source potential of said first-type fourth MOS transistor, said second and third bipolar transistors being connected in series between the power supply and the ground, for producing the result of the logical operation of the input signals, with the junction of the series connected bipolar transistors being the output terminal (OUT) of the logical circuit.
Claim 7
Dependent Claim
259 words
A logical circuit which comprises: a logical operation portion (21) consisting of first and second-type MOS transistors for performing a logical operation of input signals; an output control portion (25) having an inverter circuit portion (41) for inverting an output signal from said operational portion and the remaining circuit portion comprising a first bipolar transistor (43') connected between power supply (V DD ) and the ground and conductively controlled by the output signal from said logical operation portion, a first-type first MOS transistor (45') conductively controlled by the output signal from said inverter circuit, a first-type second MOS transistor (47') connected between an output terminal and the ground and conductively controlled by the emitter potential of said first bipolar transistor, a first-type third MOS transistor (51') conductively controlled by the output signal from said inverter circuit and a first-type fourth MOS transistor (49') conductively controlled by the output signal from said logical operational portion, said first-type third and fourth MOS transistors being connected in series between the output terminal and the ground; and an output portion (23) consisting of a second bipolar transistor (37) conductively controlled by the output signal from said inverter circuit and a third bipolar transistor (39) conductively controlled by the source potential of said first-type fourth MOS transistor, said second and third bipolar transistors being connected in series between the power supply and the ground, for producing the result of the logical operation of the input signals, with the junction of the series connected bipolar transistors being the output terminal (OUT) of the logical circuit.
Claim 8
Dependent Claim
16 words
The logical circuit as claimed in claim 5 wherein said logical circuit is a NAND circuit.
Claim 9
Dependent Claim
91 words
The logical circuit as claimed in claim 5 wherein the first and second type MOS transistors in the logical operation portion are PMOS and NMOS transistors, each gate electrode of which being connected to each of the input terminals and each of the source electrodes of the PMOS transistors is connected to the power supply, while each of the source electrodes of the NMOS transistors is connected in series to each other and each drain of the PMOS transistors is connected as a common output terminal of the logical operational portion.
Claim 10
Dependent Claim
22 words
The logical circuit as claimed in claim 5 wherein said first-type first, second, third, and fourth MOS transistors are NMOS transistors, respectively.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-03-22 | 1991-09-21 | 1992-03-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-03-22 | 1995-09-21 | 1996-03-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-03-22 | 1999-09-21 | 2000-03-22 | $7700.00 | Window Closed / Lapsed |