Synchronizer

Claim 1

A flip-flop circuit for driving an input circuit of a synchronous dynamic random access memory comprising: a) a complementary pair of data inputs (D*,D) for receiving data pulses, b) a clock input (CLK) for receiving clock pulses, c) a capture latch circuit (21) for capturing a bit, having a pair of complementary latch inputs (B,C) and a pair of complementary outputs (Q*,Q), d) means (27-32) for applying data pulses from the complementary data inputs (D*,D) to the latch inputs (B,C) of the capture latch (21), e) means (19,20,37) for triggering the capture latch (21) from the clock pulses, and f) means for connecting the complementary outputs to each other through a bidirectional holding latch (121), whereby during coincidence of a rising edge of a clock pulse and the presence of a data pulse of one polarity, the capture latch (21) is enabled to store a bit corresponding to the data pulse, and to drive the pair of complementary outputs (Q*,Q), and following said leading edge of a clock pulse and said one polarity of the data pulse the complementary outputs (Q*,Q) remain driven by the holding latch (121).