US6069504A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Adjustable output driver circuit having parallel pull-up and pull-down elements
Assignee: Round Rock Research LLC
•
Filing: 1998-09-03
•
Granted: 2000-05-30
•
Expires: 2018-09-03
Abstract
Abstract An output driver circuit offers control and logic level adjustment for high speed data communications in a synchronous memory such as a synchronous dynamic random access memory (SDRAM). Level adjustment is obtained by resistive division between a termination resistor and controllable impedances between an output node and VDD and VSS power supplies. Control functions include slew rate modification of the signal at the output node, by sequentially turning on or off output transistors in response to a transition in an input signal. Different schemes of weighting the output transistors obtains different characteristics of the output signal. Load matching circuitry and voltage level forcing circuitry is described for improving high frequency operation.
Inventors
- 👤 Brent Keeth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 13:13
CPC Classifications
G; G11; G11C; G11C7/00; H; H03; H03K; H03K17/00; H03K17/16; H03K17/161; H03K17/162; H03K17/163; H03K17/164; G11C7/10; G11C7/1051
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
158 words
An output driver circuit, comprising: a first plurality of active load devices electrically coupled between an output node and a first voltage terminal, each active load device having a control terminal; a control circuit coupled to each of the control terminals of the active load devices of the first plurality of active load devices for sequentially activating or deactivating the active load devices in response to a first input signal received by the control circuit, the control circuit having a first inverter having an output coupled to the control terminal of one of the first plurality of active load devices, a second inverter having an output coupled to an input of the first inverter; and forcing circuitry coupled to the first and second inverters to couple the output of the second inverter to either the first voltage terminal or a second voltage terminal based upon an input of the second inverter and an output of the first inverter.
Claim 2
Dependent Claim
158 words
An output driver circuit, comprising: a first plurality of active load devices electrically coupled between an output node and a first voltage terminal, each active load device having a control terminal; a control circuit coupled to each of the control terminals of the active load devices of the first plurality of active load devices for sequentially activating or deactivating the active load devices in response to a first input signal received by the control circuit, the control circuit having a first inverter having an output coupled to the control terminal of one of the first plurality of active load devices, a second inverter having an output coupled to an input of the first inverter; and forcing circuitry coupled to the first and second inverters to couple the output of the second inverter to either the first voltage terminal or a second voltage terminal based upon an input of the second inverter and an output of the first inverter.
Claim 3
Dependent Claim
29 words
The output driver circuit of claim 1, further comprising a first adjustable voltage divider circuit interposed between the first plurality of active load devices and the first voltage terminal.
Claim 4
Dependent Claim
138 words
The output driver circuit of claim 1, further comprising a second plurality of active load devices electrically coupled between the output node and the second voltage terminal, each active load device of the second plurality of active load devices having a control terminal, wherein the control circuit is further coupled to each of the control terminals of the active load devices of the second plurality of active load devices for sequentially activating or deactivating the active load devices of the second plurality of active load devices in response to a second input signal received by the control circuit, the control circuit having a third inverter having an output coupled to the control terminal of one of the second plurality of active load devices, and a fourth inverter having an output coupled to an input of the third inverter.
Claim 5
Dependent Claim
53 words
The output driver circuit of claim 3, wherein the control circuit further comprises forcing circuitry coupled to the third and fourth inverters to couple the output of the second inverter to either the first or second voltage terminals based upon an input of the fourth inverter and an output of the third inverter.
Claim 6
Dependent Claim
108 words
The output driver circuit of claim 4 wherein the forcing circuit comprises: a forcing node coupled to the output of the second inverter; first and second p-type transistors, each having a control terminal, coupled in series between the first voltage terminal and the forcing node; and first and second n-type transistors, each having a control terminal, coupled in series between the forcing node and the second voltage terminal, wherein the control terminals of the first p-type and n-type transistors are coupled to the input of the second inverter and the control terminals of the second p-type and n-type transistors are coupled to the output of the first inverter.
Claim 7
Dependent Claim
29 words
The output driver circuit of claim 3, further comprising a second adjustable voltage divider circuit interposed between the second plurality of active load devices and the second voltage terminal.
Claim 8
Dependent Claim
80 words
The output driver circuit of claim 3 wherein the first plurality of active load devices comprises n-type transistors and the second plurality of active load devices comprises p-type transistors, the output driver circuit further comprising: a plurality of p-type capacitors, each capacitor coupled between a respective control terminal of the n-type transistors and the second voltage terminal; and a plurality of n-type capacitors, each capacitor coupled between a respective control terminal of the p-type transistors and the second voltage terminal.
Claim 9
Dependent Claim
41 words
The output driver circuit of claim 1, further comprising a capacitor coupled between the output of the second inverter and the second voltage terminal for delaying the activation or deactivation of the one of the first plurality of active load devices.
Claim 10
Dependent Claim
41 words
The output driver circuit of claim 3, further comprising a capacitor coupled between the output of the fourth inverter and the second voltage terminal for delaying the activation or deactivation of the one of the second plurality of active load devices.
Claim 11
Dependent Claim
188 words
An output driver circuit, comprising: a first plurality of active load devices electrically coupled between an output node and a first voltage terminal, each active load device having a control terminal; a second plurality of active load devices electrically coupled between the output node and a second voltage terminal, each active load device having a control terminal; a control circuit coupled to the control terminals of the first and second pluralities of active load devices for sequentially activating and deactivating the active load devices of the first and second pluralities in response to an input signal, the control circuit having a first plurality of inverters, each inverter having an output coupled to a respective control terminal of the active load devices of the first and second pluralities of active load devices, and a second plurality of inverters, each inverter having an output coupled to an input of a respective one of the first plurality of inverters; and forcing circuitry coupled to the first and second plurality of inverters for selectively coupling the output of the second inverters to either the first voltage terminal or the second voltage terminal.
Claim 12
Dependent Claim
188 words
An output driver circuit, comprising: a first plurality of active load devices electrically coupled between an output node and a first voltage terminal, each active load device having a control terminal; a second plurality of active load devices electrically coupled between the output node and a second voltage terminal, each active load device having a control terminal; a control circuit coupled to the control terminals of the first and second pluralities of active load devices for sequentially activating and deactivating the active load devices of the first and second pluralities in response to an input signal, the control circuit having a first plurality of inverters, each inverter having an output coupled to a respective control terminal of the active load devices of the first and second pluralities of active load devices, and a second plurality of inverters, each inverter having an output coupled to an input of a respective one of the first plurality of inverters; and forcing circuitry coupled to the first and second plurality of inverters for selectively coupling the output of the second inverters to either the first voltage terminal or the second voltage terminal.
Claim 13
Dependent Claim
35 words
The output driver circuit of claim 10 wherein the first plurality of active load devices comprises a plurality of first-type transistors and the second plurality of active load devices comprises a plurality of second-type transistors.
Claim 14
Dependent Claim
62 words
The output driver circuit of claim 11, further comprising a plurality of second-type capacitors, each coupled between the control terminal of a respective one of the plurality of first-type transistors and the second voltage terminal, and a plurality of first-type capacitors each coupled between the control terminal of a respective one of the plurality of second-type transistors and the second voltage terminal.
Claim 15
Dependent Claim
18 words
The output driver circuit of claim 12 wherein the first-type is N-type and the second type is P-type.
Claim 16
Dependent Claim
38 words
The output driver circuit of claim 10 wherein the control circuit further comprises a plurality of capacitors, each capacitor coupled between the output of a respective one of the second plurality of inverters and the second voltage terminal.
Claim 17
Dependent Claim
46 words
The output driver circuit of claim 10, further comprising a first adjustable impedance interposed between the first plurality of active load devices and the first voltage terminal, and a second adjustable impedance interposed between the second plurality of active load devices and the second voltage terminal.
Claim 18
Independent Claim
119 words
A method for producing an output signal having a variable slew rate in response to an input signal, comprising: generating a first sequence of activation signals in response to the input signal, the first sequence of activation signals having an increasing delay with respect to the input signal; feeding forward the input signal and feeding back a respective one of the first sequence of activation signals to a forcing circuit; and applying each of the activation signals of the first sequence of activation signals to a respective control terminal of a first plurality of active load devices coupled between a first voltage terminal and an output node to sequentially activate or deactivate the first plurality of active load devices.
Claim 19
Independent Claim
119 words
A method for producing an output signal having a variable slew rate in response to an input signal, comprising: generating a first sequence of activation signals in response to the input signal, the first sequence of activation signals having an increasing delay with respect to the input signal; feeding forward the input signal and feeding back a respective one of the first sequence of activation signals to a forcing circuit; and applying each of the activation signals of the first sequence of activation signals to a respective control terminal of a first plurality of active load devices coupled between a first voltage terminal and an output node to sequentially activate or deactivate the first plurality of active load devices.
Claim 20
Dependent Claim
90 words
The method of claim 16, further comprising: generating a second sequence of activation signals in response to the complement of the input signal, the second sequence of activation signals having an increasing delay with respect to the complement of the input signal; and applying each of the activation signals of the second sequence of activation signals to a respective control terminal of a second plurality of active load devices coupled the output node and a second voltage terminal to sequentially activate or deactivate the second plurality of active load devices.
Claim 21
Dependent Claim
25 words
The method of claim 17, further comprising matching the output load of the control terminals of the first and second plurality of active load devices.
Claim 22
Dependent Claim
30 words
The method of claim 16, further comprising adjusting an impedance between a supply voltage terminal and the first voltage terminal to adjust a voltage value of the first voltage terminal.
Claim 23
Dependent Claim
28 words
The method of claim 16 wherein generating a sequence of activation signals comprises applying the input signal to a plurality of delay circuits having increasing propagation delay times.
References Cited (Backward Citations)
US4096402A
Cited
US4183095A
Cited
US4404474A
Cited
US4638187A
Cited
US4638187B1
Cited
US4789796A
Cited
US5636163A
Cited
US4758743A
Cited
US4829199A
Cited
US4984204A
Cited
US4888498A
Cited
JPH02112317A
Cited
JPH02119427A
Cited
US5055713A
Cited
EP0382124A2
Cited
US5111075A
Cited
US4992676A
Cited
US4961010A
Cited
US4958088A
Cited
US5165046A
Cited
US5179298A
Cited
US5239206A
Cited
EP0450871A2
Cited
US5513327A
Cited
US5243703A
Cited
US5473575A
Cited
US5134311A
Cited
US5001369A
Cited
JPH0490620A
Cited
JPH04135311A
Cited
US5122690A
Cited
US5349247A
Cited
US5281865A
Cited
US5128563A
Cited
US5150186A
Cited
US5128560A
Cited
US5220208A
Cited
US5194765A
Cited
US5276642A
Cited
US5440260A
Cited
JPH05136664A
Cited
US5220209A
Cited
US5498990A
Cited
US5321368A
Cited
US5355391A
Cited
US5432823A
Cited
JPH05282868A
Cited
US5361002A
Cited
US5278460A
Cited
US5254883A
Cited
US5485490A
Cited
US5274276A
Cited
EP0599631A1
Cited
US5311481A
Cited
US5347177A
Cited
JPH06282817A
Cited
US5488321A
Cited
US5347179A
Cited
US5367205A
Cited
JPH06326590A
Cited
US5506814A
Cited
US5428311A
Cited
US5451898A
Cited
EP0655741A2
Cited
US5590073A
Cited
US5574698A
Cited
US5400283A
Cited
US5438545A
Cited
US5508638A
Cited
EP0680049A2
Cited
US5661416A
Cited
US5589788A
Cited
US5457407A
Cited
US5694065A
Cited
US5619473A
Cited
US5627780A
Cited
US5719509A
Cited
WO1996010866A1
Cited
US5568077A
Cited
US5497127A
Cited
US5644252A
Cited
US5602494A
Cited
US5621690A
Cited
US5638335A
Cited
US5581197A
Cited
US5576645A
Cited
US5636173A
Cited
US5621340A
Cited
US5631872A
Cited
US5578941A
Cited
US5636174A
Cited
US5627791A
Cited
US5668763A
Cited
US5838177A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-30 | 2003-11-29 | 2004-05-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-30 | 2007-11-29 | 2008-05-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-30 | 2011-11-29 | 2012-05-30 | $7700.00 | Window Closed / Lapsed |