US4758743A
Expired / Lapsed
US
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Output buffer with improved di/dt
Assignee: NXP USA Inc
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Filing: 1986-09-26
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Granted: 1988-07-19
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Expires: 2006-09-26
Abstract
Abstract An integrated circuit comprises a chip containing electric circuits in a package with leads. The chip receives power via the leads. The leads have inductance so that when there is a change in current flow (di/dt) through a lead there is a voltage which is developed between the end of the lead and the chip which can cause the chip to either malfunction or function poorly. The highest di/dt is generally caused by an output buffer that changes the logic state of its output. The typical output buffer has a pair of driver transistors that provide one of a logic high or logic low. The di/dt generated by these transistors is controlled by controlling the voltage on the gate of the transistor which is providing the particular logic state. This control reduces di/dt from that typically provided at the very beginning of a logic state transition but increases it over that typically provided immediately thereafter for the purpose of optimizing logic state transition speed for a given maximum di/dt.
Inventors
- 👤 Sam Dehganpour
- 👤 Perry H. Pelley, III
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 21:06
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361; H03K17/00; H03K17/16; H03K17/161; H03K17/162; H03K17/163; H03K17/164
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
410 words
In an integrated circuit comprising a package and a chip containing electrical circuits, the chip characterized as being contained in the package the package characterized as having leads, wherein a first lead is connected to a first power supply terminal of the chip and a second lead is connected a second power supply terminal of the chip, the first and second leads characterized as having inductance, a buffer circuit in the chip, comprising: a first transistor having a first current electrode coupled to the first power supply terminal, a second current electrode for providing an output of the buffer circuit, and a control electrode; a second transistor having a first current electrode coupled to the control electrode of the first transistor, a control electrode for receiving a first input signal, and a second current electrode; a first resistor having a first electrode coupled to the second current electrode of the second transistor, and a second electrode coupled to the second power supply terminal; a third transistor having a first current electrode coupled to the second power supply terminal, a second current electrode coupled to the second current electrode of the first transistor, and a control electrode; a fourth transistor having a first current electrode coupled to the control electrode of the third transistor, a control electrode for receiving a second input signal complementary to the first input signal, and a second current electrode; a second resistor having a first electrode coupled to the second current electrode of the fourth transistor, and a second current electrode coupled to the second power supply terminal; a fifth transistor having a first current electrode coupled to the first power supply terminal, a second current electrode coupled to the control electrode of the first transistor, and a control electrode for receiving the first input signal; a sixth transistor having a first current electrode coupled to the first power supply terminal, a second current electrode coupled to the control electrode of the third transistor, and a control electrode for receiving the second input signal; a seventh transistor having a first current electrode coupled to the first power supply terminal, a second current electrode coupled to the second current electrode of the first transistor, and a control electrode; and a delay circuit, having an input for receiving the first input signal and an output coupled to the control electrode of the seventh transistor, for providing a time delay between the input and output of said delay circuit.
Claim 2
Dependent Claim
410 words
In an integrated circuit comprising a package and a chip containing electrical circuits, the chip characterized as being contained in the package the package characterized as having leads, wherein a first lead is connected to a first power supply terminal of the chip and a second lead is connected a second power supply terminal of the chip, the first and second leads characterized as having inductance, a buffer circuit in the chip, comprising: a first transistor having a first current electrode coupled to the first power supply terminal, a second current electrode for providing an output of the buffer circuit, and a control electrode; a second transistor having a first current electrode coupled to the control electrode of the first transistor, a control electrode for receiving a first input signal, and a second current electrode; a first resistor having a first electrode coupled to the second current electrode of the second transistor, and a second electrode coupled to the second power supply terminal; a third transistor having a first current electrode coupled to the second power supply terminal, a second current electrode coupled to the second current electrode of the first transistor, and a control electrode; a fourth transistor having a first current electrode coupled to the control electrode of the third transistor, a control electrode for receiving a second input signal complementary to the first input signal, and a second current electrode; a second resistor having a first electrode coupled to the second current electrode of the fourth transistor, and a second current electrode coupled to the second power supply terminal; a fifth transistor having a first current electrode coupled to the first power supply terminal, a second current electrode coupled to the control electrode of the first transistor, and a control electrode for receiving the first input signal; a sixth transistor having a first current electrode coupled to the first power supply terminal, a second current electrode coupled to the control electrode of the third transistor, and a control electrode for receiving the second input signal; a seventh transistor having a first current electrode coupled to the first power supply terminal, a second current electrode coupled to the second current electrode of the first transistor, and a control electrode; and a delay circuit, having an input for receiving the first input signal and an output coupled to the control electrode of the seventh transistor, for providing a time delay between the input and output of said delay circuit.
Claim 3
Dependent Claim
82 words
The buffer circuit of claim 1 wherein the delay circuit comprises: an eighth transistor having a first current electrode coupled to the second power supply terminal, a second current electrode coupled to the control electrode of the seventh transistor, and a control electrode; and a delay portion, having an input for receiving the first input signal and an output coupled to the control electrode of the eighth transistor, for providing a time delay between the input and output of said delay portion.
Claim 4
Dependent Claim
67 words
The buffer circuit of claim 2 further comprising: an inverter having an input coupled to the first current electrode of the fourth transistor, and an output; and a ninth transistor having a control electrode coupled to the output of the inverter, a first current electrode coupled to the second power supply terminal, and a second current electrode coupled to the second current electrode of the third transistor.
Claim 5
Dependent Claim
27 words
The buffer circuit of claim 3 further comprising a third resistor interposed between the first current electrode of the first transistor and the first power supply terminal.
Claim 6
Dependent Claim
27 words
The buffer circuit of claim 4 further comprising a fourth resistor interposed between the first current electrode of the third transistor and the second power supply terminal.
Claim 7
Dependent Claim
274 words
In an integrated circuit comprising a chip containing electrical circuits contained in a package having leads, wherein a first lead is connected to a first power supply terminal of the chip and a second lead is connected to a second power supply terminal of the chip, the first and second leads characterized as having inductance, a buffer circuit in the chip for providing an output on an output terminal at a logic state representative of buffer signal, comprising: driver means, coupled to the first power supply terminal and having an input, for providing current from the first power supply terminal to the output terminal in proportion to a voltage level on said input; a first resistor having a first terminal coupled to the second power supply terminal, and a second terminal; a first transistor having a control electrode for receiving a first data signal, a first current electrode coupled to the second terminal of the first resistor, and a second current electrode coupled to the input of the driver means; a second transistor having a first current electrode coupled to the first power supply terminal, a control electrode for receiving the first data signal, and a second current electrode coupled to the input of the driver means; a third transistor having a first current electrode coupled to the first power supply terminal, a second current electrode coupled to the output terminal, and a control electrode; and a delay circuit, having an input for receiving the first input signal and an output coupled to the control electrode of the third transistor, for providing a time delay between the input and output of said delay circuit.
Claim 8
Dependent Claim
274 words
In an integrated circuit comprising a chip containing electrical circuits contained in a package having leads, wherein a first lead is connected to a first power supply terminal of the chip and a second lead is connected to a second power supply terminal of the chip, the first and second leads characterized as having inductance, a buffer circuit in the chip for providing an output on an output terminal at a logic state representative of buffer signal, comprising: driver means, coupled to the first power supply terminal and having an input, for providing current from the first power supply terminal to the output terminal in proportion to a voltage level on said input; a first resistor having a first terminal coupled to the second power supply terminal, and a second terminal; a first transistor having a control electrode for receiving a first data signal, a first current electrode coupled to the second terminal of the first resistor, and a second current electrode coupled to the input of the driver means; a second transistor having a first current electrode coupled to the first power supply terminal, a control electrode for receiving the first data signal, and a second current electrode coupled to the input of the driver means; a third transistor having a first current electrode coupled to the first power supply terminal, a second current electrode coupled to the output terminal, and a control electrode; and a delay circuit, having an input for receiving the first input signal and an output coupled to the control electrode of the third transistor, for providing a time delay between the input and output of said delay circuit.
Claim 9
Dependent Claim
82 words
The buffer circuit of claim 6 wherein the delay circuit comprises: a fourth transistor having a first current electrode coupled to the second power supply terminal, a second current electrode coupled to the control electrode of the third transistor, and a control electrode; and a delay portion, having an input for receiving the first input signal and an output coupled to the control electrode of the fourth transistor, for providing a time delay between the input and output of said delay portion.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-07-19 | 1992-01-18 | 1992-07-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-07-19 | 1996-01-18 | 1996-07-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-07-19 | 2000-01-18 | 2000-07-19 | $7700.00 | Window Closed / Lapsed |