Integrated logic circuit incorporating a module which generates a control signal that cancels switching noise

Claim 2

A circuit having reduced susceptibility to switching noise including: a plurality of logic gate means for generating and switching logic signals on respective output conductors; a plurality of driver means having control terminals respectively coupled to said output conductors; a current bus coupled to said plurality of driver means; each driver means operating to pass a large current from said bus in response to a logic one signal on its control terminal and to pass a small current in response to a logic zero; said bus having a parasitic inductance which generates a noise signal when said switching logic signals cause current on said bus to change in magnitude; a parasitic capacitive coupling from said bus to the control terminal of each driver means which couples a portion of said noise signal on said bus to the control terminals; and a noise reducing module coupled to the control terminal of each driver means; said module including a common bus and a plurality of capacitors having one terminal coupled to the control terminal of a respective driver means and having another terminal coupled to said common bus.

Claim 3

A circuit according to claim 1 wherein said noise reducing module further includes respective resistors in series with each of said capacitors.

Claim 4

A circuit according to claim 2 wherein each resistor in said module is less than twenty ohms.

Claim 5

A circuit according to claim 1 wherein said noise reducing module further includes an inductor in series with said common bus.

Claim 6

A circuit according to claim 3 wherein said inductor in said module is less than four nanohenrys.

Claim 7

A circuit according to claim 1 wherein each capacitor in said noise reducing module is less than ten picofarads.

Claim 8

A circuit according to claim 1 wherein said circuit is integrated on a single semiconductor substrate.

Claim 9

A circuit according to claim 1 wherein the number of logic gate means is at least twenty and number of driver means is at least twenty.

Claim 10

A circuit according to claim 1 wherein said logic gate means and driver means are comprised of transistors of a type selected from the group of PNP, NPN and MOS.

Claim 11

A circuit according to claim 1 wherein said logic gates are current mode logic gates, and each driver means is a single NPN transistor.

Claim 12

A circuit having reduced susceptibility to switching noise including: a plurality of logic gate means for generating and switching logic signals on respective output conductors; a plurality of driver means having control terminals respectively coupled to said output conductors; a current bus coupled to said plurality of driver means; each driver means operating to pass a large current from said bus in response to a logic one signal on its control terminal and to pass a small current in response to a logic zero; a said bus having a parasitic inductance which generates a noise signal when said switching logic signals cause current on said bus to change in magnitude; a parasitic capacitive coupling from said bus to the control terminal of each driver means which couples a portion of said noise signal on said bus to the control terminals; and a noise reducing means coupled to the control terminal of each driver means for generating, from the logic signals that switch, a control signal that is similar in shape and opposite in polarity to said noise signal on said bus, and for coupling said control signal to said control terminals to cancel the noise signal which is parasitically coupled thereto.

Claim 13

A circuit having reduced susceptibility to switching noise including: a plurality of logic gate means for generating and switching logic signals on respective output conductors; a plurality of driver means having control terminals respectively coupled to said output conductors; a current bus coupled to said plurality of driver means; each driver means operating to pass a large current from said bus in response to a logic one signal on its control terminal and to pass a small current in response to a logic zero; a said bus having a parasitic inductance which generates a noise signal when said switching logic signals cause current on said bus to change in magnitude; a parasitic capacitive coupling from said bus to the control terminal of each driver means which couples a portion of said noise signal on said bus to the control terminals; and a noise reducing means coupled to the control terminal of each driver means for generating, from the logic signals that switch, a control signal that is similar in shape and opposite in polarity to said noise signal on said bus, and for coupling said control signal to said control terminals to cancel the noise signal which is parasitically coupled thereto.

Claim 14

A circuit according to claim 11 wherein said noise reducing means generates said control signal as two concatenated pulses one of which is positive and the other of which is negative.

Claim 17

A method according to claim 13 wherein said control signal is generated as two concatenated pulses one of which is positive and the other of which is negative.