EP0054642A2
Expired / Lapsed
EP
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Noise clamping circuit
Assignee: International Business Machines Corp
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Filing: 1981-10-09
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Granted: —
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Expires: 2001-10-09
Abstract
Abstract A clamping circuit to reduce self-induced switching noise in a multi-chip module semiconductor structure. A module section interconnects the chips (Chip 1, Chip 2) and the chips have a power supply (V cc ) and power leads respectively. An impedance path is defined between each of the chips (Chip 1, Chip 2) and the power supply (V cc ) to define a current path for switching noise through the top of the module. A high impedance path is defined for voltages below a predetermined upper limit (V1) of the chip supply voltage and a low impedance path is defined by the clamping circuit for the voltage range where noise superimposed on the chip supply voltage occurs.
Inventors
- 👤 Evan Ezra Davidson
- 👤 George Alexander Katopis
- 👤 Barry Jay Rubin
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 16:11
CPC Classifications
G; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/462; G05F1/467
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
140 words
Noise clamping circuit in a monolithic integrated semiconductor structure having a pair of semiconductor chips each having a pair of power leads, one chip (Chip 1) defining a driver communicating with a second chip (Chip 2; defining a receiver, a module section interconnecting said pair of chips, said module section having a signal plane and two reference planes on either side of said plane, a pair of power vias (V cc , VR) disposed under said pair of chips, characterized by a top surface module decoupling capacitance, synthesized within the existing chip technology as impedance means for reducing self-induced switching noise in said semiconductor structure; said means interposed between said pair of chip power leads of each chip defining on-chip impedance characteristic interconnecting the power vias (V , V R ) for allowing module currents to complete current loops on-chip.
Claim 2
Dependent Claim
140 words
Noise clamping circuit in a monolithic integrated semiconductor structure having a pair of semiconductor chips each having a pair of power leads, one chip (Chip 1) defining a driver communicating with a second chip (Chip 2; defining a receiver, a module section interconnecting said pair of chips, said module section having a signal plane and two reference planes on either side of said plane, a pair of power vias (V cc , VR) disposed under said pair of chips, characterized by a top surface module decoupling capacitance, synthesized within the existing chip technology as impedance means for reducing self-induced switching noise in said semiconductor structure; said means interposed between said pair of chip power leads of each chip defining on-chip impedance characteristic interconnecting the power vias (V , V R ) for allowing module currents to complete current loops on-chip.
Claim 3
Dependent Claim
23 words
The device as claimed in claim 1, characterized by a low impedance current path for switching noise near the top of the module.
Claim 4
Independent Claim
70 words
The device as claimed in claims 1 and/or 2, characterized by means (Fig. 2) interposed between said power supply (V ) and said chip defining a high impedance current path for voltages below a predetermined upper limit of chip supply voltage and a low impedance path for a voltage range where noise superimposed upon said chip supply voltage occurs thereby defining a current path through the top of said module.
Claim 5
Dependent Claim
59 words
The device as claimed in at least claim 3, characterized in that said means in the form of a cir- . cuit (Fig. 4) comprises a transistor (T1), first and second series coupled resistors (R1, R2) in parallel with said transistor (T1) and a diode (D1) in parallel with one of said resistors (R1, R2) and said transistor (Tl).
Claim 6
Independent Claim
67 words
The device as claimed in at least claims 3 and 4, characterized in that a high impedance path is created by the series combination of said first and second resistors (R1, R2) for voltage levels below a predetermined first upper limit (V1), and a low impedance path created above the first upper limit (V1) in a linear region where said transistor (T1) and diode (D1) are conducting.
Claim 7
Independent Claim
37 words
The device as claimed in claims 4 and 5, characterized in that said predetermined upper limit (V1) is a function of the resistance values of a voltage divider formed by said first and second resistors (R1, R2).
Claim 8
Dependent Claim
46 words
The device as claimed in at least claim 4, characterized in that said transistor (T1) has a base-emitter junction N times larger than the area of said diode (D1) and a gain defined by the current mirror effect between said transistor (T1) and said diode (D1).
Claim 9
Dependent Claim
60 words
The device as claimed in at least claim 4, further characterized by a third resistor (R3) in series with said transistor (T1) and wherein said third resistor (R3) defines the saturation point of said transistor (T1) and above the said saturation point a high impedance path is defined by the parallel combination of said first and third resistors (R1, R3).
Claim 10
Dependent Claim
85 words
The device as claimed in at least claim 3, characterized in that said means interposed comprises a parallel circuit comprising first and second parallel resistors (R1, R2 and R3, R4), a pair of diodes in series with a second resistor (R2), a third resistor (R3) in series with a first resistor (R1), an output terminal (OV) between said first and third resistors (R1, R3) and, a fourth resistor (R4) coupled in series with a third diode that is in parallel with said third resistor (R2).
References Cited (Backward Citations)
No citation records indexed.
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