US5970240A
Expired / Lapsed
US
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Method and apparatus for configurable memory emulation
Assignee: Cadence Design Systems Inc
•
Filing: 1997-06-25
•
Granted: 1999-10-19
•
Expires: 2017-06-25
Abstract
Abstract A configurable method and apparatus for implementing the various large memory instances commonly found in a user's design in a hardware logic emulation system is disclosed. No external boards or systems are required to implement typical memory instances. The method and apparatus sorts the memory instances in the user's input design, packing as many memory instances as possible into a physical RAM on the emulation boards. The method also counts the number of physical RAMs necessary to implement the plurality of memory instances. The method maps the memory instances into physical RAMs, and routes the address, data and control signals and controller circuit into a programmable logic chip.
Inventors
- 👤 Tao Shinn Chen
- 👤 Dam Van Bui
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 06:16
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/0223; G06F12/0292
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
139 words
A unified configurable memory architecture for emulation comprising: a physical memory divided into a plurality of segments; and a programmable logic chip coupled to said physical memory and implementing a controller function, said controller function comprising: a set associative memory coupled to said physical memory, where said set associative memory maps at least one of a plurality of sets into a least one of said plurality of segments; an address input multiplexer for processing addresses associated with said plurality of sets, and switching one of said addresses onto main address lines; a data input multiplexer for processing a plurality of data lines associated with said plurality of sets, and switching one of said plurality of data lines onto main data lines; and a sequencer, for providing time slots for said plurality of sets, coupled to said set associative memory.
Claim 2
Dependent Claim
139 words
A unified configurable memory architecture for emulation comprising: a physical memory divided into a plurality of segments; and a programmable logic chip coupled to said physical memory and implementing a controller function, said controller function comprising: a set associative memory coupled to said physical memory, where said set associative memory maps at least one of a plurality of sets into a least one of said plurality of segments; an address input multiplexer for processing addresses associated with said plurality of sets, and switching one of said addresses onto main address lines; a data input multiplexer for processing a plurality of data lines associated with said plurality of sets, and switching one of said plurality of data lines onto main data lines; and a sequencer, for providing time slots for said plurality of sets, coupled to said set associative memory.
Claim 3
Dependent Claim
19 words
The apparatus of claim 1 wherein said programmable logic chip is further coupled to a plurality of multiplexer chips.
Claim 4
Dependent Claim
18 words
The apparatus of claim 1 wherein said physical memory is further coupled to a plurality of multiplexer chips.
Claim 5
Dependent Claim
32 words
The apparatus of claim 1 wherein said programmable logic chip may be reconfigured to implement a portion of the logic of the user's input design when a memory function is not required.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-10-18 | 2003-04-19 | 2003-10-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-10-18 | 2007-04-19 | 2007-10-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-10-18 | 2011-04-19 | 2011-10-19 | $7700.00 | Window Closed / Lapsed |