Patent US2895535A successfully refreshed from Google Patents.
Patent US5663080A successfully refreshed from Google Patents.
US5663080A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for manufacturing MOS-type integrated circuits
Assignee: STMicroelectronics SRL
•
Filing: 1995-09-06
•
Granted: 1997-09-02
•
Expires: 2015-09-06
Abstract
Abstract A process for producing integrated circuits including the steps of: selectively growing field insulating regions of insulating material extending partly inside a substrate having a given type of conductivity; depositing a polycrystalline silicon layer on the substrate; shaping the polycrystalline silicon layer through a mask; and selectively implanting ions of the same conductivity type as the substrate, using the shaping mask, through the field insulating regions. The implanted ions penetrate the substrate and form channel stopper regions beneath the field insulating regions.
Inventors
- 👤 Manlio Sergio Cereda
- 👤 Giancarlo Ginami
- 👤 Enrico Laurin
- 👤 Andrea Ravaglia
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 03:22
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/40; H10B41/42; H10B41/49; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0188; H10D84/02; H10D84/03; H10D84/038; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0125; H10W10/0126; H10W10/0127; H10W10/10; H10W10/13
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
188 words
A method for producing a MOS transistor and a memory cell array on a common substrate comprising the steps of: selectively growing field insulating regions of insulating material to extend partly within the common substrate in a MOS transistor area and a memory cell array area; depositing a first layer of semiconductive material on the substrate across the MOS transistor area and the memory cell array area; patterning the first semiconductive layer using a mask; selectively implanting ions of a first conductivity type through the mask and the field insulating regions and into the substrate for forming channel stopper regions beneath the field insulating regions in the MOS transistor area and the memory cell array area; depositing an electrically insulating layer on the first semiconductive layer in the MOS transistor area and the memory cell array area; removing the electrically insulating layer only from the MOS transistor area; and depositing a second semiconductive layer on the first semiconductive layer and the electrically insulating layer such that the electrically insulating layer will insulate the first semiconductive layer from the second semiconductive layer only in the memory cell array area.
Claim 2
Independent Claim
188 words
A method for producing a MOS transistor and a memory cell array on a common substrate comprising the steps of: selectively growing field insulating regions of insulating material to extend partly within the common substrate in a MOS transistor area and a memory cell array area; depositing a first layer of semiconductive material on the substrate across the MOS transistor area and the memory cell array area; patterning the first semiconductive layer using a mask; selectively implanting ions of a first conductivity type through the mask and the field insulating regions and into the substrate for forming channel stopper regions beneath the field insulating regions in the MOS transistor area and the memory cell array area; depositing an electrically insulating layer on the first semiconductive layer in the MOS transistor area and the memory cell array area; removing the electrically insulating layer only from the MOS transistor area; and depositing a second semiconductive layer on the first semiconductive layer and the electrically insulating layer such that the electrically insulating layer will insulate the first semiconductive layer from the second semiconductive layer only in the memory cell array area.
Claim 3
Dependent Claim
24 words
A method as claimed in claim 1 wherein the step of depositing a first layer of semiconductive material includes the step of depositing polycrystalline.
Claim 4
Dependent Claim
23 words
A method as claimed in claim 2 wherein the step of patterning includes using the mask having openings over the field insulating regions.
Claim 5
Dependent Claim
24 words
A method as claimed in claim 1 further including, after the step of depositing a second semiconductive layer, the step of: shaping gate regions.
Claim 6
Dependent Claim
14 words
A method as claimed in claim 4 wherein the second semiconductive layer includes polycrystalline.
Claim 7
Dependent Claim
12 words
A method as claimed in claim 5 wherein the ions include Boron.
Claim 8
Independent Claim
209 words
A method for producing a MOS transistor and a memory cell array on a common substrate, the method comprising the steps of: selectively growing field insulating regions of insulating material to extend partly within the common substrate of a semiconductive material having a first type of conductivity in a MOS transistor area and a memory cell array area; depositing a first layer of semiconductive polycrystalline material on the substrate across the MOS transistor area and the memory cell array area; patterning the first semiconductive polycrystalline layer using a mask; selectively implanting ions of the first conductivity type through the mask and the field insulating regions and into the substrate for forming channel stopper regions beneath the field insulating regions in the MOS transistor area and the memory cell array area; depositing an electrically insulating oxide layer on the first semiconductive polycrystalline layer in the MOS transistor area and the memory cell array area; removing the electrically insulating oxide layer only from the MOS transistor area; and depositing a second semiconductive polycrystalline layer on the first semiconductive polycrystalline layer and the electrically insulating oxide layer such that the electrically insulating oxide layer will insulate the first semiconductive layer from the second semiconductive layer only in the memory cell array area.
Claim 9
Independent Claim
209 words
A method for producing a MOS transistor and a memory cell array on a common substrate, the method comprising the steps of: selectively growing field insulating regions of insulating material to extend partly within the common substrate of a semiconductive material having a first type of conductivity in a MOS transistor area and a memory cell array area; depositing a first layer of semiconductive polycrystalline material on the substrate across the MOS transistor area and the memory cell array area; patterning the first semiconductive polycrystalline layer using a mask; selectively implanting ions of the first conductivity type through the mask and the field insulating regions and into the substrate for forming channel stopper regions beneath the field insulating regions in the MOS transistor area and the memory cell array area; depositing an electrically insulating oxide layer on the first semiconductive polycrystalline layer in the MOS transistor area and the memory cell array area; removing the electrically insulating oxide layer only from the MOS transistor area; and depositing a second semiconductive polycrystalline layer on the first semiconductive polycrystalline layer and the electrically insulating oxide layer such that the electrically insulating oxide layer will insulate the first semiconductive layer from the second semiconductive layer only in the memory cell array area.
Claim 10
Dependent Claim
18 words
A method as claimed in claim 7 wherein the mask presents openings corresponding with the field insulating regions.
Claim 11
Dependent Claim
27 words
A method as claimed in claim 7 further including, after the step of depositing a second layer of semiconductive polycrystalline material, the step of: patterning gate regions.
Claim 12
Dependent Claim
21 words
A method as claimed in claim 9 wherein the first type of conductivity is P type and the ions include Boron.
Claim 13
Independent Claim
216 words
A method for producing N and P channel devices including a MOS transistor and a memory cell array on a common substrate, the method comprising the steps of: selectively growing field insulating regions of insulating material to extend partly within the common substrate having a first portion with a first type of conductivity and a second portion with a second type of conductivity across a MOS transistor area and memory cell array area; depositing a first layer of semiconductive polycrystalline material on the substrate; patterning the first semiconductive polycrystalline layer using a mask having openings over field insulating regions within the first portion of the substrate and covering the second portion of the substrate; implanting ions through the mask and field insulating regions and into the substrate for forming channel stopper regions beneath the field insulating regions; depositing an electrically insulating oxide layer on the first semiconductive polycrystalline layer in the MOS transistor area and the memory cell array area; removing the electrically insulating oxide layer only from the MOS transistor area; and depositing a second semiconductive polycrystalline layer on the first semiconductive polycrystalline layer and the electrically insulating oxide layer such that the electrically insulating oxide layer will insulate the first semiconductive layer from the second semiconductive layer only in the memory cell array area.
Claim 14
Independent Claim
216 words
A method for producing N and P channel devices including a MOS transistor and a memory cell array on a common substrate, the method comprising the steps of: selectively growing field insulating regions of insulating material to extend partly within the common substrate having a first portion with a first type of conductivity and a second portion with a second type of conductivity across a MOS transistor area and memory cell array area; depositing a first layer of semiconductive polycrystalline material on the substrate; patterning the first semiconductive polycrystalline layer using a mask having openings over field insulating regions within the first portion of the substrate and covering the second portion of the substrate; implanting ions through the mask and field insulating regions and into the substrate for forming channel stopper regions beneath the field insulating regions; depositing an electrically insulating oxide layer on the first semiconductive polycrystalline layer in the MOS transistor area and the memory cell array area; removing the electrically insulating oxide layer only from the MOS transistor area; and depositing a second semiconductive polycrystalline layer on the first semiconductive polycrystalline layer and the electrically insulating oxide layer such that the electrically insulating oxide layer will insulate the first semiconductive layer from the second semiconductive layer only in the memory cell array area.
Claim 15
Dependent Claim
30 words
A method as claimed in claim 11 further including, after the step of depositing a second layer of semiconductive polycrystalline material, the step of: patterning gate regions of the devices.
Claim 16
Dependent Claim
12 words
A method as claimed in claim 12 wherein the ions include Boron.
References Cited (Backward Citations)
US3319311A
Cited
US3434019A
Cited
US3461360A
Cited
US3950777A
Cited
US3764396A
Cited
GB1372086A
Cited
US3821776A
Cited
US3845495A
Cited
US3849216A
Cited
US3924265A
Cited
US4001860A
Cited
US3909320A
Cited
US3986903A
Cited
JPS5148981A
Cited
US4015278A
Cited
JPS5185381A
Cited
US4072975A
Cited
JPS5366181A
Cited
US4055884A
Cited
US4145700A
Cited
JPS5374385A
Cited
US4190850A
Cited
US4145703A
Cited
JPS53135284A
Cited
JPS54885A
Cited
US4148047A
Cited
CA1123119A
Cited
CA1136291A
Cited
US4376286A
Cited
US5338961A
Cited
US4376286B1
Cited
US4344081A
Cited
US4593302A
Cited
US4593302B1
Cited
US4680853A
Cited
US4549193A
Cited
US4399449A
Cited
US4412242A
Cited
JPS59178746A
Cited
US5098855A
Cited
US5194924A
Cited
US4918501A
Cited
US4663645A
Cited
US4719184A
Cited
EP0206929A1
Cited
US4798810A
Cited
US4786614A
Cited
US5004701A
Cited
JPH01283944A
Cited
JPH02203520A
Cited
US4931408A
Cited
EP0428283A2
Cited
US5153143A
Cited
JPH0422170A
Cited
US5192707A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-01 | 2001-03-03 | 2001-09-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-01 | 2005-03-03 | 2005-09-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-01 | 2009-03-03 | 2009-09-02 | $7700.00 | Window Closed / Lapsed |