Plural polygon source pattern for mosfet

Claim 2

A high power MOSFET device; said device comprising a wafer of semiconductor material of one of the conductivity types and having a first surface and a parallel second surface; said first surface having a large plurality of highly packed, equally spaced symme-trically disposed polygonal base regions of the opposite conductivity type to said one of the conductivity types therein; each of said base regions having respective polygonal source regions of said one of the conductivity types disposed therein and extending to said first surface; a gate insulation layer on said first surface and disposed between said source regions; and a gate electrode on said gate insulation layer; a drain electrode on said second surface; a single, continuous source electrode means connected to said polygonal source regions; a respective ring-shaped channel means disposed between the outer periphery of each of said polygonal source regions and the outer periphery of its said respective base region and beneath said gate insulation layer; each of said polygonal base regions having outer sides which are parallel to respective sides of adjacent ones of said plurality of polygonal base regions; said parallel sides being laterally spaced from one another by respective common regions which are centrally disposed beneath said gate insulation layer and which are of said one of the conductivity types; a relatively high resistivity region of said one of the conductivity types underlying said common regions and being continuous with said common regions; said common regions having a substantially higher conductivity than said underlying region; said common regions and said underlying region being in series in the current path from said continuous source electrode means to said drain electrode; said parallel outer sides of said polygonal base regions being as close to one another as possible to produce a high packing density.

Claim 3

The device of claim 1, wherein the outer peripheries of each of said base regions and each of said source regions are hexagonal.

Claim 4

The device of claim 1 or 2, wherein each of said polygonal base regions has a relatively deep central region and a relatively shallow outer region; each of said polygonal source regions being ring-shaped; each of said relatively shallow outer regions underlying their said respective ring-shaped source region.

Claim 5

A MOSFET device formed by D-MOS manufactur-ing techniques comprising, in combination: a semiconductor chip; a large plurality of highly packed, symmetri-cally disposed, polygonal source regions disposed on one surface of said chip and source electrode means connected to said source regions; said chip having a bottom surface; said bottom surface having a drain electrode connected thereto; a gate electrode disposed between said spaced source regions and disposed on an insulating layer on top of said chip; each of the sides of each of said polygonal source regions being parallel to a respective side of an adjacent one of said polygonal source regions; said sides being as close to one another as possible to produce a high packing density; a plurality of pairs of first and second channels disposed between said adjacent sides of each of said source regions; said pairs of first and second channels being of a first conductivity type and being capable of inversion to a second conductivity type by a gate bias; said pairs of first and second channels having spaced outer sides which extend into respective common semiconductor regions beneath said gate insulation layer; the inner sides of said first and second channels connected to respective source electrode means; said common semiconductor region defining a current path across the thickness of said chip and having a high conductivity adjacent said surface of said chip and a low conductivity, necessary for reverse voltage withstand ability, extending to a depth greater than about 1 micron below said surface, whereby said high conductivity region of said common region substantially decreases the on-resistance of said device.

Claim 6

A MOSFET device formed by D-MOS manufactur-ing techniques comprising, in combination: a semiconductor chip; a large plurality of highly packed, symmetri-cally disposed, polygonal source regions disposed on one surface of said chip and source electrode means connected to said source regions; said chip having a bottom surface; said bottom surface having a drain electrode connected thereto; a gate electrode disposed between said spaced source regions and disposed on an insulating layer on top of said chip; each of the sides of each of said polygonal source regions being parallel to a respective side of an adjacent one of said polygonal source regions; said sides being as close to one another as possible to produce a high packing density; a plurality of pairs of first and second channels disposed between said adjacent sides of each of said source regions; said pairs of first and second channels being of a first conductivity type and being capable of inversion to a second conductivity type by a gate bias; said pairs of first and second channels having spaced outer sides which extend into respective common semiconductor regions beneath said gate insulation layer; the inner sides of said first and second channels connected to respective source electrode means; said common semiconductor region defining a current path across the thickness of said chip and having a high conductivity adjacent said surface of said chip and a low conductivity, necessary for reverse voltage withstand ability, extending to a depth greater than about 1 micron below said surface, whereby said high conductivity region of said common region substantially decreases the on-resistance of said device.

Claim 7

The MOSFET device of claim 4, wherein said first and second channels are the end regions of respective, relative-ly deep regions which extend away from one another and which have large outer radii of curvature.

Claim 8

The device of claim 4 or 5, wherein said source regions are hexagonal.

Claim 9

The device of claim 1, wherein there are in excess of about 1,000 polygonal source regions each having a width of about 1 mil.

Claim 10

The device of claim 7, wherein there are in excess of about 1,000 hexagonal source regions each having a width of about 1 mil.

Claim 11

A high power MOSFET device having a large number of parallel-connected individual FET devices closely packed into a relatively small area comprising: a thin wafer of monocrystalline semiconductor material having first and second spaced, parallel surfaces; at least a first portion of the thickness of said water which extends from said first surface having a resistivity of a value characterized by a lightly doped epitaxially deposited region of one of the conductivity types; a plurality of symmetrically disposed, laterally distributed hexagonal regions having a conductivity type opposite that of said one type, each extending into said first portion of said wafer for given depths and extending to said first surface; said hexagonal regions spaced from one another by a symmetric hexagonal lattice of the material of said first portion; each side of each of said hexagonal regions being parallel to and adjacent the side of another of said hexagonal regions; a respective hexagonal annular source region of said one of the conductivity types formed in the outer peripheral regions of said each of said hexagonal regions and extending downwardly from said first surface; the outer rim of each of said annular source regions being annularly spaced from the outer periphery of its said respective hexagonal region to form an annular channel between each of said annular source regions and the adjacent said hexagonal lattice of the material of said first portion of said wafer which is disposed between said hexagonal regions; a single common source electrode formed in said first surface and connected to each of said source regions; a single drain electrode connected to said second surface of said wafer; an insulation layer means on said first surface and overlying said hexagonal lattice of material disposed between said hexagonal regions and said annular channels; and a gate electrode atop said insulation layer means and operable to control the formation of an inversion layer in said annular channels.

Claim 12

A high power MOSFET device having a large number of parallel-connected individual FET devices closely packed into a relatively small area comprising: a thin wafer of monocrystalline semiconductor material having first and second spaced, parallel surfaces; at least a first portion of the thickness of said water which extends from said first surface having a resistivity of a value characterized by a lightly doped epitaxially deposited region of one of the conductivity types; a plurality of symmetrically disposed, laterally distributed hexagonal regions having a conductivity type opposite that of said one type, each extending into said first portion of said wafer for given depths and extending to said first surface; said hexagonal regions spaced from one another by a symmetric hexagonal lattice of the material of said first portion; each side of each of said hexagonal regions being parallel to and adjacent the side of another of said hexagonal regions; a respective hexagonal annular source region of said one of the conductivity types formed in the outer peripheral regions of said each of said hexagonal regions and extending downwardly from said first surface; the outer rim of each of said annular source regions being annularly spaced from the outer periphery of its said respective hexagonal region to form an annular channel between each of said annular source regions and the adjacent said hexagonal lattice of the material of said first portion of said wafer which is disposed between said hexagonal regions; a single common source electrode formed in said first surface and connected to each of said source regions; a single drain electrode connected to said second surface of said wafer; an insulation layer means on said first surface and overlying said hexagonal lattice of material disposed between said hexagonal regions and said annular channels; and a gate electrode atop said insulation layer means and operable to control the formation of an inversion layer in said annular channels.

Claim 13

The MOSFET device of claim 9, wherein said gate electrode is of polysilicon material.

Claim 14

The MOSFET device of claim 9, which includes more than 1,000 individual parallel-connected devices formed in said wafer, each of which occupies a total lateral area having a diameter less than about 1 mil. and are spaced from one another by about 0.6 mil.

Claim 15

The MOSFET device of claim 9, 10 or 11, wherein the portions of said hexagonal lattice which extend from said first surface for a depth less than the depth of said hexagonal regions have a relatively high conductivity compared to the conductivity of said first portion of said wafer.