Semiconductor device and method of producing the same

Claim 2

A semiconductor device comprising: a first MISFET having a gate electrode and a semiconductor region as a source or drain region, said semiconductor region comprising a first semiconductor region and a second semiconductor region, the second semiconductor region being formed between said gate electrode and said first semiconductor region, said second semiconductor region having a lower impurity concentration than that of said first semiconductor region; and a plurality of second MISFETs, each having a gate electrode structure and a semiconductor region as a source or drain region, each to be used as a memory cell, the plurality of second MISFETs being arrayed in a matrix, said gate electrode structure comprising a first gate electrode and a second gate electrode formed over and aligned with said first gate electrode, said second gate electrode being made of a double-layer film comprising a first film of polycrystalline silicon and a second film of a material selected from the group consisting of refractory metals and platinum and silicides of refractory metals and platinum, opposed peripheral sides of at least said first gate electrode being covered with a dense silicon oxide insulating film, said silicon oxide insulating film being a thermal oxide film, so as to improve the charge retention characteristics of the first gate electrode as compared to charge retention characteristics of the first gate electrode without the dense insulating film, each of said dense insulating films on opposed peripheral sides of the first gate electrode being covered with a respective sidewall insulation film, said semiconductor region comprising a third semiconductor region and a fourth semiconductor region, the fourth semiconductor region being formed between said third semiconductor region and said gate electrode structure, wherein said first, second, third and fourth semiconductor regions all have the same conductivity type, wherein said fourth semiconductor region of each said second MISFET is formed substantially in alignment with the first and second gate electrodes of said second MISFET, wherein said second semiconductor region is formed substantially in alignment with said gate electrode of said first MISFET, wherein said first semiconductor region is formed substantially in alignment with a sidewall insulation film formed on a side of the gate electrode of the first MISFET, wherein the third semiconductor region is formed in alignment with a sidewall insulation film covering a dense insulating film covering a peripheral side of a first gate electrode, and wherein said fourth semiconductor region has a lower impurity concentration than that of said third semiconductor region.

Claim 3

A semiconductor device according to claim 1 wherein the impurity concentration of said first semiconductor region is substantially the same as that of said third semiconductor region.

Claim 4

A semiconductor device according to claim 2 wherein said second and fourth semiconductor regions are doped with phosphorus and arsenic, respectively.

Claim 5

A semiconductor device according to claim 1 wherein said second and fourth semiconductor regions are shallower than said first and third semiconductor regions, respectively.

Claim 6

A semiconductor device according to claim 1 further comprising P-channel MISFETs, each having a gate electrode and a semiconductor region as a source or drain region, and wherein said first and second MISFETs are N-channel MISFETs.

Claim 7

A semiconductor device provided with a memory cell array comprising memory cells arrayed in a matrix and with a peripheral circuit, said semiconductor device comprising: at least one first MISFET constituting said peripheral circuit, and having a gate electrode and semiconductor regions as source or drain regions; a plurality of word lines extending in said memory cell array in a first direction; a plurality of data lines extending in said memory cell array in a second direction to cross said word lines; and second MISFETs constituting said memory cells, each of said second MISFETs having a gate electrode structure and semiconductor regions as source or drain regions, said gate electrode structure comprising a first gate electrode and a second gate electrode formed over and aligned with said first gate electrode, said second gate electrode being made of a double-layer film comprising a first film of polycrystalline silicon and a second film of a material selected from the group consisting of refractory metals and platinum and silicides of refractory metals and platinum, opposed peripheral sides of at least said first gate electrode being covered with a dense silicon oxide insulating film, said silicon oxide insulating film being a thermal oxide film, so as to improve the charge retention characteristics of the first gate electrode as compared to charge retention characteristics of the first gate electrode without the dense insulating film, each of the dense insulating films on opposed peripheral sides of the first gate electrode being covered with a respective sidewall insulation film, one of said semiconductor regions being connected to said data lines, and said second gate electrode being formed integrally with said word lines, wherein said semiconductor regions of said first and second MISFETs are each comprised of a first semiconductor region and a second semiconductor region, the second semiconductor region of each semiconductor region of the second MISFETs being formed between said first semiconductor region and said gate electrode structure, the second semiconductor region of the first MISFET being formed between said first semiconductor region of the first MISFET and said gate electrode, said second semiconductor region having a lower impurity concentration than that of said first semiconductor region, wherein said first and second semiconductor regions of said first and second MISFETs are all of the same conductivity type, wherein said second semiconductor regions of said second MISFETs are formed substantially in alignment with the first and second gate electrodes, wherein said second semiconductor region of said first MISFET is formed substantially in alignment with gate electrode of said first MISFET, wherein said first semiconductor region of said first MISFET is formed substantially in alignment with a sidewall insulation film formed on a side of the gate electrode of the first MISFET, and wherein the first semiconductor regions of the second MISFETs are formed substantially in alignment with sidewall insulation films covering the dense insulating films.

Claim 8

A semiconductor device provided with a memory cell array comprising memory cells arrayed in a matrix and with a peripheral circuit, said semiconductor device comprising: at least one first MISFET constituting said peripheral circuit, and having a gate electrode and semiconductor regions as source or drain regions; a plurality of word lines extending in said memory cell array in a first direction; a plurality of data lines extending in said memory cell array in a second direction to cross said word lines; and second MISFETs constituting said memory cells, each of said second MISFETs having a gate electrode structure and semiconductor regions as source or drain regions, said gate electrode structure comprising a first gate electrode and a second gate electrode formed over and aligned with said first gate electrode, said second gate electrode being made of a double-layer film comprising a first film of polycrystalline silicon and a second film of a material selected from the group consisting of refractory metals and platinum and silicides of refractory metals and platinum, opposed peripheral sides of at least said first gate electrode being covered with a dense silicon oxide insulating film, said silicon oxide insulating film being a thermal oxide film, so as to improve the charge retention characteristics of the first gate electrode as compared to charge retention characteristics of the first gate electrode without the dense insulating film, each of the dense insulating films on opposed peripheral sides of the first gate electrode being covered with a respective sidewall insulation film, one of said semiconductor regions being connected to said data lines, and said second gate electrode being formed integrally with said word lines, wherein said semiconductor regions of said first and second MISFETs are each comprised of a first semiconductor region and a second semiconductor region, the second semiconductor region of each semiconductor region of the second MISFETs being formed between said first semiconductor region and said gate electrode structure, the second semiconductor region of the first MISFET being formed between said first semiconductor region of the first MISFET and said gate electrode, said second semiconductor region having a lower impurity concentration than that of said first semiconductor region, wherein said first and second semiconductor regions of said first and second MISFETs are all of the same conductivity type, wherein said second semiconductor regions of said second MISFETs are formed substantially in alignment with the first and second gate electrodes, wherein said second semiconductor region of said first MISFET is formed substantially in alignment with gate electrode of said first MISFET, wherein said first semiconductor region of said first MISFET is formed substantially in alignment with a sidewall insulation film formed on a side of the gate electrode of the first MISFET, and wherein the first semiconductor regions of the second MISFETs are formed substantially in alignment with sidewall insulation films covering the dense insulating films.

Claim 9

A semiconductor device according to claim 6 wherein the impurity concentration of said first semiconductor region of said first MISFET is substantially the same as that of said first semiconductor region of said second MISFET.

Claim 10

A semiconductor device according to claim 7 wherein said second semiconductor regions of said first and second MISFETs are doped with phosphorus and arsenic, respectively.

Claim 11

A semiconductor device according to claim 6 wherein said second semiconductor regions of said first and second MISFETs are shallower than said first semiconductor regions of said first and second MISFETs, respectively.

Claim 12

A semiconductor device according to claim 6 further comprising P-channel MISFETs, each having a gate electrode and a semiconductor region as source or drain region, and wherein said first and second MISFETs are N-channel MISFETs.

Claim 13

A semiconductor device according to claim 1 wherein said silicon oxide films formed by thermal oxidation each have a thickness of 300Å to 500Å.

Claim 14

A semiconductor device according to claim 1 wherein said sidewall insulating films covering said dense insulating films are formed on opposed peripheral sides of said first and second gate electrodes of said second MISFETs.

Claim 15

A semiconductor device according to claim 12 wherein said dense insulating films cover opposed peripheral sides of both said first and second gate electrodes of said second MISFETs.

Claim 16

A semiconductor device according to claim 1 wherein said sidewall insulation films are silicon oxide films formed by chemical vapor deposition.

Claim 17

A semiconductor device according to claim 6 wherein said silicon oxide films formed by thermal oxidation each have a thickness of 300Å to 500Å.

Claim 18

A semiconductor device according to claim 33 wherein said sidewall insulating films covering said dense insulating films are formed on opposed peripheral sides of said first and second gate electrodes of said second MISFETs.

Claim 19

A semiconductor device according to claim 12 wherein said dense insulating films cover opposed peripheral sides of both said first and second gate electrodes of said second MISFETs.

Claim 20

A semiconductor device according to claim 6 wherein said sidewall insulation films are silicon oxide films formed by chemical vapor deposition.