Planar structure for high voltage semiconductor devices with gaps in glassy layer over high field regions

Claim 1

A high voltage semiconductor device comprising a chip of semiconductor material; at least one P-N junction formed in at least one surface of said chip; electrode means connected to at least a selected area of said surface whereby, upon application of a reverse-biasing voltage to said electrode means, an electric field is produced in said chip of semiconductor material; a thin glassy layer of insulation material overlying and sealing at least portions of said one surface of said chip; a second insulation layer of material which is not subject to polarization effects disposed between said glassy layer and said first surface of said chip; said glassy layer being polarizable by electric fields having at least a component parallel to said thin glassy layer; and first and second coextensive spaced elongated gaps in said glassy layer to reduce polarization effects therein and to reduce the adverse influence of polarization adjacent said gaps on the electric field within said chip under reverse-bias conditions; a guard ring formed in said first surface of said chip closely adjacent to but spaced from the outer periphery of said chip; said guard ring having a conductivity type opposite to that of the chip in which said guard ring is formed; said first and second gaps being located above and extending along opposite sides respectively of said guard ring.