Thyristor containing channel stopper

Claim 1

A thyristor comprising: (a) a semiconductor body comprising first and second opposite major surfaces, (b) at least four successive regions of alternating conductivity types arranged in said semiconductor body between said first and second major surfaces, which four regions comprise first and second surface-layer regions of one conductivity type which adjoin, respectively, said first and second major surfaces of the body, a third inner-layer region which separates said first and second regions, is of opposite conductivity type and forms first and second p,n junctions with respectively said first and second regions, and a fourth surface region which is provided in said first region adjacent said first major surface, which fourth region is of said opposite conductivity type and forms a third p,n junction with said first region, (c) a first annular moat located in said first major surface of said body and containing passivating dielectric material therein, said first annular moat laterally bounding said first region and said first p,n junction terminating at said first moat and being passivated by said dielectric material in said first moat, (d) a further region of said one conductivity type laterally bounding said third region and merging with said second region to extend said second p,n junction toward said first major surface, (e) a second annular moat located in said first major surface of said body, said second moat having an outer periphery spaced from the periphery of the body, the second annular moat extending around said first annular moat and containing passivating dielectric material therein, said second p,n junction terminating at the dielectric material at the outer periphery of said second moat and being passivated by said dielectric material in said second moat, (f) a highly-doped surface region of said opposite conductivity type located at said first major surface between said first and second moats to form a channel stopper located between and spaced from the terminations of said first and second p,n junctions at, respectively, said first and second moats, (g) a control electrode connected to said first region and located at said first surface, (h) a first electrode connected to said fourth region and located at said first surface, and (i) a second electrode connected to said second region and located at said second surface.