US5477167A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable application specific integrated circuit using logic circuits to program antifuses therein
Assignee: QuickLogic Corp
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Filing: 1995-01-27
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Granted: 1995-12-19
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Expires: 2015-01-27
Abstract
Abstract A programmable ASIC architecture allows the size of programming transistors to be reduced along with other parts of the device as advances in processing technology are made. Programming enable circuits are used to allow a programming address shift register having fewer bits to be used in the programming of antifuses. Methods of simultaneously programming multiple corresponding antifuses to speed ASIC programming are disclosed. Aspects of the architecture allow output protection for digital logic elements in modules to be eliminated, some testing transistors to be eliminated, the sizes of other testing transistors to be reduced, capacitances on interconnect wire segments to be reduced, some programming transistors to be eliminated, and the sizes of other programming transistors to be reduced.
Inventors
- 👤 Hua-Thye Chua
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 12:46
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/17758; G; G11; G11C; G11C17/00; G11C17/14; G11C17/18; H03K19/17704; H03K19/17724; H03K19/17728; H03K19/1778; H03K19/17792
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
117 words
A method, comprising: (a) using a digital logic element in a module of a programmable device to sink an antifuse programming current from a first wire segment of said programmable device to an output terminal of said digital logic element, no isolating transistor which is nonconductive during antifuse programming being coupled to said output terminal; (b) supplying a programming voltage V1 to source said antifuse programming current onto a second wire segment to program an antifuse contacting said first and second wire segments; and (c) using said digital logic element to generate a digital logic signal during normal operation of said programmable device, said digital logic signal having a maximum voltage V2, V1 being greater than V2.
Claim 2
Independent Claim
117 words
A method, comprising: (a) using a digital logic element in a module of a programmable device to sink an antifuse programming current from a first wire segment of said programmable device to an output terminal of said digital logic element, no isolating transistor which is nonconductive during antifuse programming being coupled to said output terminal; (b) supplying a programming voltage V1 to source said antifuse programming current onto a second wire segment to program an antifuse contacting said first and second wire segments; and (c) using said digital logic element to generate a digital logic signal during normal operation of said programmable device, said digital logic signal having a maximum voltage V2, V1 being greater than V2.
Claim 3
Dependent Claim
37 words
The method of claim 1, wherein V1 is approximately 12 volts, V2 is within a range of approximately 3 volts to approximately 5 volts, said antifuse comprises amorphous silicon, and said antifuse programming current exceeds 10 milliamperes.
Claim 4
Dependent Claim
30 words
The method of claim 1, wherein said digital logic element is supplied with a supply voltage during step (a), said supply voltage being substantially greater than said maximum voltage V2.
Claim 5
Independent Claim
78 words
A method, comprising: during programming of a programmable logic device, supplying a voltage VCC1 to a digital logic element in a module of a macrocell, an output terminal of said digital logic element sinking a programming current through an antifuse of said macrocell to program said antifuse; and during normal circuit operation of said programmable logic device, supplying a voltage VCC2 to said digital logic element in said module of said macrocell, VCC2 being substantially less than VCC1.
Claim 6
Independent Claim
78 words
A method, comprising: during programming of a programmable logic device, supplying a voltage VCC1 to a digital logic element in a module of a macrocell, an output terminal of said digital logic element sinking a programming current through an antifuse of said macrocell to program said antifuse; and during normal circuit operation of said programmable logic device, supplying a voltage VCC2 to said digital logic element in said module of said macrocell, VCC2 being substantially less than VCC1.
Claim 7
Dependent Claim
54 words
The method of claim 4, wherein said voltage VCC2 is supplied to said digital logic element during a first time period of said programming of said programmable logic device, and wherein said voltage VCC1 is supplied to said digital logic element during a second time period of said programming of said programmable logic device.
Claim 8
Dependent Claim
27 words
The method of claim 4, wherein said voltage VCC1 is approximately 7.5 volts and said voltage VCC2 is in an approximate range of 3 to 5 volts.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-18 | 1999-06-19 | 1999-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-18 | 2003-06-19 | 2003-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-18 | 2007-06-19 | 2007-12-19 | $7700.00 | Window Closed / Lapsed |