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US5384500A
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Programmable logic device macrocell with an exclusive feedback and an exclusive external input line for a combinatorial mode and accommodating two separate programmable or planes
Assignee: Micron Technology Inc
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Filing: 1993-12-22
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Granted: 1995-01-24
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Expires: 2013-12-22
Abstract
Abstract A programmable logic device (PLD) with an output macrocell circuit is disclosed. Specifically, there is a macrocell having an exclusive logic signal feedback line and an exclusive external input signal line both feeding into the input of the PLD. Exactly, this PLD can disable the I/O pad and still have an internal feedback to its logic circuitry.
Inventors
- 👤 Mark A. Hawes
- 👤 Paul S. Zagar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:33
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1737; H03K19/177; H03K19/17704; H03K19/17708
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
313 words
A programmable logic device comprising: a) an AND array having multiple inputs and multiple product term outputs; b) first and second OR arrays, each OR array receiving, as inputs, product term outputs from the AND array, each OR array having a single sum-of products output; and c) an output macrocell having c1) a first input for receiving the sum-of-products output from the first OR array; c2) a second input for receiving the sum-of-products output from the second OR array; c3) a third input for receiving a single product term output from the AND array; 4) means for generating a registered signal, said means for generating having a first input coupled to the sum-of-products output of said first OR array, and a second input coupled to a clock signal; c5) a first multiplexer having a first input for receiving the registered signal, and a second input for receiving a non-registered signal derived from the sum-of-products term output of said second OR array, said first multiplexer having an output, and being operable so as to select between the registered signal and the non-registered signal, and providing the signal so selected at its output; c6) a tri-statable gate which either couples the selected signal to an input/output terminal or decouples the selected signal from the input/output terminal; c7) a logic gate having an output, a first input coupled to the sum-of-products term output of said first OR array, and a second input coupled to the single product term output from the AND array; and c8) a second multiplexer having an output coupled to at least one of said inputs of said AND array, said second multiplexer also having first and second inputs, said first input being coupled to the output of said first multiplexer, and said second input being coupled to the input/output terminal, said second multiplexer being controlled by the output of said logic gate.
Claim 2
Dependent Claim
313 words
A programmable logic device comprising: a) an AND array having multiple inputs and multiple product term outputs; b) first and second OR arrays, each OR array receiving, as inputs, product term outputs from the AND array, each OR array having a single sum-of products output; and c) an output macrocell having c1) a first input for receiving the sum-of-products output from the first OR array; c2) a second input for receiving the sum-of-products output from the second OR array; c3) a third input for receiving a single product term output from the AND array; 4) means for generating a registered signal, said means for generating having a first input coupled to the sum-of-products output of said first OR array, and a second input coupled to a clock signal; c5) a first multiplexer having a first input for receiving the registered signal, and a second input for receiving a non-registered signal derived from the sum-of-products term output of said second OR array, said first multiplexer having an output, and being operable so as to select between the registered signal and the non-registered signal, and providing the signal so selected at its output; c6) a tri-statable gate which either couples the selected signal to an input/output terminal or decouples the selected signal from the input/output terminal; c7) a logic gate having an output, a first input coupled to the sum-of-products term output of said first OR array, and a second input coupled to the single product term output from the AND array; and c8) a second multiplexer having an output coupled to at least one of said inputs of said AND array, said second multiplexer also having first and second inputs, said first input being coupled to the output of said first multiplexer, and said second input being coupled to the input/output terminal, said second multiplexer being controlled by the output of said logic gate.
Claim 3
Dependent Claim
344 words
A programmable logic device comprising: (a) an AND array having multiple inputs and multiple product term outputs; (b) a first OR array having a first single sum-of-products output, and also having multiple inputs comprising a plurality of product term outputs from said AND array; (c) a second OR array having a second single sum-of-products output, and also having multiple inputs comprising a plurality of product term outputs from said AND array; (d) means for receiving a clock signal; (e) an output macrocell having; (1) a first macrocell input corresponding to said first single sum-of-products output; (2) a second macrocell input corresponding to said second single sum-of-products output; (3) a third macrocell input corresponding to a single product term output from said AND array, said single product term output also serving as one of said plurality of inputs to said second OR array; (4) means for generating a registered signal, said means for generating having at least first and second inputs, the first input of said means for generating being coupled to said first single sum-of-products output, and the second input of said means for generating being coupled to said clock signal; (5) a first multiplexer for selecting between the registered signal and a non-registered signal derived from said second single sum-of-products output, said first multiplexer having an output providing a signal so selected; (6) a tri-statable gate which either couples the selected signal to an input/output terminal or decouples the selected signal from the input/output terminal, said tri-statable gate being controlled by said single product term outlet; (7) a logic gate having an output, a first input coupled to said first single sum-of-products output, and a second input coupled to said single product term output; and (8) a second multiplexer having an output coupled to at least one of said inputs of said AND array, and first and second inputs, said first input being coupled to the output of said first multiplexer, and said second input being coupled to the input/output terminal, said second multiplexer being controlled by the output of said logic gate.
Claim 4
Dependent Claim
344 words
A programmable logic device comprising: (a) an AND array having multiple inputs and multiple product term outputs; (b) a first OR array having a first single sum-of-products output, and also having multiple inputs comprising a plurality of product term outputs from said AND array; (c) a second OR array having a second single sum-of-products output, and also having multiple inputs comprising a plurality of product term outputs from said AND array; (d) means for receiving a clock signal; (e) an output macrocell having; (1) a first macrocell input corresponding to said first single sum-of-products output; (2) a second macrocell input corresponding to said second single sum-of-products output; (3) a third macrocell input corresponding to a single product term output from said AND array, said single product term output also serving as one of said plurality of inputs to said second OR array; (4) means for generating a registered signal, said means for generating having at least first and second inputs, the first input of said means for generating being coupled to said first single sum-of-products output, and the second input of said means for generating being coupled to said clock signal; (5) a first multiplexer for selecting between the registered signal and a non-registered signal derived from said second single sum-of-products output, said first multiplexer having an output providing a signal so selected; (6) a tri-statable gate which either couples the selected signal to an input/output terminal or decouples the selected signal from the input/output terminal, said tri-statable gate being controlled by said single product term outlet; (7) a logic gate having an output, a first input coupled to said first single sum-of-products output, and a second input coupled to said single product term output; and (8) a second multiplexer having an output coupled to at least one of said inputs of said AND array, and first and second inputs, said first input being coupled to the output of said first multiplexer, and said second input being coupled to the input/output terminal, said second multiplexer being controlled by the output of said logic gate.
References Cited (Backward Citations)
US3287702A
Cited
US3287703A
Cited
US3296426A
Cited
US3423646A
Cited
US3313926A
Cited
US3473160A
Cited
US3462742A
Cited
US3535498A
Cited
US3514543A
Cited
US3602733A
Cited
US3566153A
Cited
US3702985A
Cited
US3737866A
Cited
US3757306A
Cited
US3774171A
Cited
US3798606A
Cited
US3818252A
Cited
US3816725A
Cited
US3818452A
Cited
GB1444084A
Cited
US3803587A
Cited
US3769525A
Cited
US3795901A
Cited
US3792242A
Cited
US3832489A
Cited
US3849638A
Cited
US3983538A
Cited
US3990045A
Cited
US3987410A
Cited
US3912947A
Cited
US3924243A
Cited
US3906255A
Cited
US3974366A
Cited
US3979730A
Cited
US4218740A
Cited
US4037089A
Cited
US3987286A
Cited
US3967059A
Cited
US4034356A
Cited
US4034349A
Cited
US4091359A
Cited
US4107785A
Cited
US4078259A
Cited
US4093998A
Cited
US4044312A
Cited
US4124899B1
Cited
US4124899A
Cited
US4128873A
Cited
US4422072A
Cited
US4717912A
Cited
US4554640A
Cited
US5027315A
Cited
US4742252A
Cited
US4963768A
Cited
US4758746A
Cited
US4763020A
Cited
US4763020B1
Cited
US4771285A
Cited
US5168177A
Cited
US4789951A
Cited
US4918641A
Cited
US4847612A
Cited
US4879481A
Cited
US5059828A
Cited
US5012135A
Cited
US4967107A
Cited
US5027011A
Cited
US5028821A
Cited
US5055718A
Cited
US5136188A
Cited
US5166556A
Cited
US5121006A
Cited
US5247195A
Cited
US5148391A
Cited
US5287017A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-23 | 1998-07-25 | 1999-01-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-23 | 2002-07-25 | 2003-01-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-23 | 2006-07-25 | 2007-01-24 | $7700.00 | Window Closed / Lapsed |