Programmable logic array circuit having a gate to control an output condition state of a latch thereof

Claim 2

A programmable logic array circuit comprising: means for decoding a prescribed signal after a first precharge timing; means for latching an output signal from said decoder means immediately before a second precharge timing; and gating means for controlling a passage of a output from said latching means therethrough with a predetermined timing signal.

Claim 3

A programmable logic array circuit according to claim 1, wherein said decoding means comprises a NAND circuit which is comprised of a plurality of MOS transistors serially connected; said MOS transistors including an enhancement MOS transistor and a depletion MOS transistor; the gates of said MOS transistors being connected so as to receive an instruction code.

Claim 4

A programmable logic array circuit according to claim 1, wherein said latching means comprises an inverter having an input for receiving an output from the decoding means and a MOS transistor having a gate connected to the output of the inverter, a first electrode connected to the input of the inverter and a second electrode connected to a fixed potential.

Claim 5

A programmable logic array circuit according to claim 1, wherein said latching means comprises a D-type flip flop.

Claim 6

A programmable logic array circuit according to claim 1, wherein said gating means comprises an AND gate.

Claim 7

A programmable logic array system comprising: decoding means having a plurality of input lines and a plurality of output lines, said decoding means for decoding an instruction from an instruction register so as to select a specific one of said plurality of output lines during a first precharging period and for performing a logical operation between the specific output line and a timing signal from a timing and control circuit during the first timing period; a wired logical circuit connected to said plurality of the output lines of the decoding means; a plurality of sense amplifying means each connected to one of the plurality of output lines of the decoding means for amplifying an output from the wired logical circuit; a plurality of latching means respectively connected to said plurality of sense amplifiers for latching an output from said decoding means immediately before a second precharging operation; and a plurality of logical circuits connected to the latching means for controlling an output operation of the latching means by a prescribed timing signal.

Claim 8

A programmable logic array system comprising: decoding means having a plurality of input lines and a plurality of output lines, said decoding means for decoding an instruction from an instruction register so as to select a specific one of said plurality of output lines during a first precharging period and for performing a logical operation between the specific output line and a timing signal from a timing and control circuit during the first timing period; a wired logical circuit connected to said plurality of the output lines of the decoding means; a plurality of sense amplifying means each connected to one of the plurality of output lines of the decoding means for amplifying an output from the wired logical circuit; a plurality of latching means respectively connected to said plurality of sense amplifiers for latching an output from said decoding means immediately before a second precharging operation; and a plurality of logical circuits connected to the latching means for controlling an output operation of the latching means by a prescribed timing signal.

Claim 9

A programmable logic array circuit comprising: a decoder configured to decode a prescribed signal in response to a first precharge signal, the decoder having an output providing an output signal; a latch coupled to the decoder and configured to latch the decoder output signal prior to a second precharge timing signal; and a logic gate circuit coupled to the latch and configured to pass an output in response to a predetermined timing signal.

Claim 10

A programmable logic array circuit comprising: a decoder configured to decode a prescribed signal in response to a first precharge signal, the decoder having an output providing an output signal; a latch coupled to the decoder and configured to latch the decoder output signal prior to a second precharge timing signal; and a logic gate circuit coupled to the latch and configured to pass an output in response to a predetermined timing signal.