US4912348A — Method for designing pass transistor asynchronous…

Claim 1

Independent Claim 181 words

A method for designing an asynchronous sequential circuit comprising a pass transistor network, including the steps of: (a) generating a flow table indicative of the desired characteristics of the circuit, and encoding each present state variable, y i , of the flow table with a state assignment; and (b) generating from the encoded flow table a circuit design for each next state variable, Y i , of the circuit, wherein each said circuit design corresponds to a portion of the pass transistor network receiving a set of 1 input signals I j , and wherein each said partial circuit design has form ##EQU26## where p k I j (x kj ) represents a pass transistor path which decodes a transition path to a stable state S k under one of said input signals I j , bit x kj is the jth bit of state S k , each p k is a partition of the present state variables under said input signal I j , and m j is the number of partitions under said input signal I j .

Claim 2

Independent Claim 181 words

A method for designing an asynchronous sequential circuit comprising a pass transistor network, including the steps of: (a) generating a flow table indicative of the desired characteristics of the circuit, and encoding each present state variable, y i , of the flow table with a state assignment; and (b) generating from the encoded flow table a circuit design for each next state variable, Y i , of the circuit, wherein each said circuit design corresponds to a portion of the pass transistor network receiving a set of 1 input signals I j , and wherein each said partial circuit design has form ##EQU26## where p k I j (x kj ) represents a pass transistor path which decodes a transition path to a stable state S k under one of said input signals I j , bit x kj is the jth bit of state S k , each p k is a partition of the present state variables under said input signal I j , and m j is the number of partitions under said input signal I j .

Claim 3

Dependent Claim 43 words

The method of claim 1, wherein the step (b) is performed in such a manner that each said partial circuit design has identical form, except that each said partial circuit design has a different set of input signals, I j (x kj ).

Claim 4

Dependent Claim 23 words

The method of claim 1, wherein step (a) includes the operation of encoding the flow table with a single transition time state assignment.

Claim 5

Dependent Claim 276 words

The method of claim 1, wherein the circuit is a critical race free pass transistor asynchronous sequential circuit, the circuit also comprises a buffer without a long-term-memory, for receiving the output of the pass transistor network, wherein step (a) includes the operation of encoding the flow table with a single transition time state assignment, and wherein step (b) includes the operations of: (c) generating each partition p k of the circuit's present state variables under each input signal I j of the flow table, each said partition being associated with a stable internal state of the circuit, and each said partition including a block corresponding to a transition pair or k-set of said stable internal state; (d) for each state variable index, i, each said partition p k , and each input signal I j , if the ith bit in the stable state of p k for input signal I j is equal to one, including the term p k I j (1) in the design for next state variable Y i , and if the ith bit in the stable state of p k for input signal I j is equal to zero, including the term p k I j (0) in the design for next state variable Y i ; and (e) generating a state variable product expression for each partition p k , by producing a covering by said each partition p k of the transition path to the stable state of said each partition p k , and substituting the state variable product expressions for the corresponding partitions p k in the designs for the next state variables Y i .

Claim 6

Dependent Claim 31 words

The method of claim 1, also including the step of: (f) constructing the pass transistor asynchronous sequential circuit in accordance with the designs for the next state variables Y i .

Claim 7

Dependent Claim 68 words

The method of claim 1, wherein the circuit includes an input section for receiving the input signals, a logic section including a pass transistor matrix for implementing the flow table, and a buffer section for receiving output signals emerging from the logic section, and wherein step (f) includes the steps of: connecting the input section to the logic section; and connecting the buffer section to the logic section.

Claim 8

Dependent Claim 49 words

The method of claim 6, wherein the circuit also includes a feedback section for receiving buffered signals emerging from the buffer section and routing them to the logic section, and wherein step (f) includes the step of: connecting the feedback section between the buffer section and the logic section.

Claim 9

Dependent Claim 53 words

The method of claim 7, wherein the circuit also includes metal lines connecting the feedback section with the buffer section, and a gate line feeding each pass transistor, and wherein step (f) includes the step of: programming the logic section by connecting each feedback line with at least one of the gate lines.

Claim 10

Dependent Claim 19 words

The method of claim 6, including the step of: programming the pass transistor matrix with a diffusion-contact-metal transistor structure.

Claim 11

Dependent Claim 18 words

The method of claim 6, including the step of: programming the pass transistor matrix with a metal jumper.

Claim 12

Dependent Claim 292 words

The method of claim 1, wherein the circuit is an asynchronous circuit comprising an enable pass transistor network, a disable pass transistor network, and a memory-containing buffer for receiving the output of both pass transistor networks, wherein step (a) includes the operation of encoding the flow table with a single transition time state assignment, and wherein step (b) includes the operations of: (c) generating each partition p k of the circuit's present state variables under each input variable I j of the flow table, each said partition being associated with a stable internal state of the circuit, and each said partition including a block corresponding to a transition pair or k-set of said stable internal state; (d) for each state variable index, i, each said partition p k , and each input variable I j , if the block of the partition p k corresponds to a transition path in which present state variable bit y i undergoes a transition from zero to one, including the term p k I j (1) in the design for next state variable Y i , and if the block of the partition p k corresponds to a transition path in which present state variable bit y i undergoes a transition from one to zero, including the term p k I j (0) in the design for next state variable Y i ; and (e) generating a state variable product expression for each partition p k , by producing a covering by said each partition p k of the transition path to the stable state of said each partition p k , and substituting the state variable product expressions for the corresponding partitions p k in the designs for the next state variables Y i .

Claim 13

Dependent Claim 13 words

The method of claim 11, wherein the memory-containing buffer is a latching buffer.

Claim 14

Dependent Claim 354 words

The method of claim 1, wherein the circuit is a critical race free, asynchronous circuit comprising an enable pass transistor network, a disable pass transistor network, and a memory-containing buffer for receiving the output of both pass transistor networks, wherein the enable and disable pass transistor networks present a high impedance to the buffer, wherein the design for each next state variable Y i includes a term of form p k I j (x kj ) only for each pass transistor path which decodes a transition path to a stable state S k under an input I j in which a present state variable y i undergoes a change in value, and wherein step (b) includes the operations of: (c) generating each partition p k of the circuit's present state variables under each input signal I j , each said partition being associated with a stable internal state of the circuit, and each said partition including a block corresponding to a transition pair or k-set of said stable internal state; (d) for each state variable index, i, each said partition p k , and each input signal I j , if the block of the partition p k corresponds to a transition path in which present state variable bit y i undergoes a transition from zero to one, including the term p k I j (1) in the design for next state variable Y i , and if the block of the partition p k corresponds to a transition path in which present state variable bit y i undergoes a transition from one to zero, including the term p k I j (0) in the design for next state variable Y i ; and (e) generating a state variable product expression for each partition p k , by producing a covering by said each partition p k of only the portion of the transition path to the stable state of said each partition p k which contains an unstable state, and substituting the state variable product expressions for the corresponding partitions p k in the designs for the next state variables Y i .

Claim 15

Dependent Claim 63 words

The method of claim 13, wherein the flow table comprises states S i for each input signal I j , where i is a non-negative integer less than or equal to n, and wherein step (a) includes the operation of encoding the flow table with a one-hot-code state assignment with present state variable y i equal to one in state S i .

Claim 16

Dependent Claim 89 words

The method of claim 14, wherein step (b) includes the operations of: for each state transition from unstable state S k to state S i under input signal I j , including the enable term y k I j (1) in the design for next state variable Y i ; and for each state transition from unstable state S p to unstable state S j under input signal I k , including the disable term y i I k (0) in the design for next state Y i .

Claim 17

Dependent Claim 29 words

The method of claim 14, wherein the circuit is constrained to operate in a non-normal mode in which only one state variable is allowed to change at a time.

Claim 18

Dependent Claim 28 words

The method of claim 14, wherein the circuit is constrained to operates in a non-normal mode in which two state variable changes are required for each state transition.

Claim 19

Dependent Claim 119 words

The method of claim 17, wherein step (b) includes the operations of: for each internal state S i of the flow table that is stable under input signal I j , and for each state transition from unstable state S k to state S i , including the enable term y k I j (1) in the design for the next state variable Y i ; and for each internal state S j of the flow table that is unstable under input signal I j , and for each state transition from stable state S i to state S j , including the disable term y i y j (0) in the design for next state Y i .

Claim 20

Dependent Claim 108 words

The method of claim 17, wherein step (b) includes the operations of: for each internal state S i of the flow table that is stable under input signal I j , and for each state transition from unstable state S k to state S i , including the enable term y k I j (1) in the design for next state variable Y i ; and for each state transition from stable state S i to unstable state S k caused by input signal I m , including the disable term y i y k I m (0) in the design for next state variable Y i .

Claim 21

Dependent Claim 175 words

An asynchronous sequential circuit for receiving a set of 1 input signals, I j , and implementing a function defined by a flow table, where each present state variable, y i , of the flow table is encoded with a state assignment, including: a pass transistor network consisting of network portions, where each of the network portions determines one of a set of next state variables Y i in response to the status of the present state variables and the input signals, and where each network portion has a design of form ##EQU27## where p k I j (x kj ) represents a pass transistor path which decodes a transition path to a stable state S k of the circuit under one of the input signals I j , bit x kj is the jth bit of the state S k , each p k is a partition of the present state variables under said input signal I j , and m j is the number of partitions under said input signal I j .

Claim 22

Dependent Claim 175 words

An asynchronous sequential circuit for receiving a set of 1 input signals, I j , and implementing a function defined by a flow table, where each present state variable, y i , of the flow table is encoded with a state assignment, including: a pass transistor network consisting of network portions, where each of the network portions determines one of a set of next state variables Y i in response to the status of the present state variables and the input signals, and where each network portion has a design of form ##EQU27## where p k I j (x kj ) represents a pass transistor path which decodes a transition path to a stable state S k of the circuit under one of the input signals I j , bit x kj is the jth bit of the state S k , each p k is a partition of the present state variables under said input signal I j , and m j is the number of partitions under said input signal I j .

Claim 23

Dependent Claim 32 words

The circuit of claim 20, wherein each of the pass transistor network portions has identical structure, but each of the pass transistor network portions may receive a different set of input signals.

Claim 24

Dependent Claim 18 words

The circuit of claim 20, wherein the flow table is encoded with a single transition time state assignment.

Claim 25

Dependent Claim 49 words

The circuit of claim 20, wherein the circuit is a critical race free pass transistor asynchronous sequential circuit, wherein the flow table is encoded with a single transition time state assignment, and also including: a buffer, without a long-term memory, for receiving the output of the pass transistor network.

Claim 26

Dependent Claim 205 words

The circuit of claim 23, wherein a state variable product expression is substituted for each partition p k in the design of each network portion, where each said state variable product expression corresponds to a covering by each said partition p k of the transition path to the stable state of said each partition p k , each said partition p k of the circuit's present state variables under each input variable I j of the flow table is associated with a stable internal state of the circuit, and each said partition p k includes a block corresponding to a transition pair or k-set of said stable internal state, and where the design for each next state variable Y i includes the term p k I j (1) for each state variable index, i, each said partition p k , and each input variable I j , if the ith bit in the stable state of p k for input variable I j is equal to one, and the design for each next state variable Y i includes the term p k I j (0) if the ith bit in the stable state of p k for input variable I j is equal to zero.

Claim 27

Dependent Claim 41 words

The circuit of claim 20, also including: an input section connected to the pass transistor network, for receiving the input signals; and a buffer section connected to the pass transistor network, for receiving output signals emerging from the pass transistor network.

Claim 28

Dependent Claim 37 words

The circuit of claim 25, also including: a feedback section connected between the buffer section and the pass transistor network, for receiving buffered signals emerging from the buffer section and routing them to the pass transistor network.

Claim 29

Dependent Claim 46 words

The circuit of claim 26, also including: metal lines for connecting the feedback section with the buffer section; and a gate line feeding each pass transistor in the pass transistor network, and wherein each feedback line is connected with at least one of the gate lines.

Claim 30

Dependent Claim 17 words

The circuit of claim 25, wherein the pass transistor network is programmable with a diffusion-contact-metal transistor structure.

Claim 31

Dependent Claim 16 words

The circuit of claim 25, wherein the pass transistor network is programmable with a metal jumper.

Claim 32

Dependent Claim 254 words

The circuit of claim 20, wherein the pass transistor network includes an enable pass transistor network and a disable transistor network, wherein the flow table is encoded with a single transition time state assignment, and also including: a memory-containing buffer for receiving the output of the enable pass transistor network and the disable pass transistor network; and wherein a state variable product expression is substituted for each partition p k in the design of each network portion, where each said state variable product expression corresponds to a covering by said each partition p k of the transition path to the stable state of said each partition p k , wherein each partition p k of the circuit's present state variables under each input variable I j of the flow table is associated with a stable internal state of the circuit, and each said partition p k includes a block corresponding to a transition pair or k-set of said stable internal state, and where the design for each next state variable Y i includes the term p k I j (1) if the block of the partition p k corresponds to a transition path in which present state variable bit y i undergoes a transition from zero to one, where the design for each next state variable Y i includes the term p k I j (0) if the block of the partition p k corresponds to a transition path in which present state variable bit y i undergoes a transition from one to zero.

Claim 33

Dependent Claim 13 words

The circuit of claim 30, wherein the memory-containing buffer is a latching buffer.

Claim 34

Dependent Claim 70 words

The circuit of claim 20, wherein the circuit is a critical race free, asynchronous circuit, and wherein the pass transistor network includes an enable pass transistor network and a disable pass transistor network, and also including: a memory-containing buffer for receiving the output of the enable pass transistor network and the disable pass transistor network, wherein the enable and disable pass transistor networks present a high impedance to the buffer.

Claim 35

Dependent Claim 268 words

The circuit of claim 32, wherein the design for each next state variable Y i includes a term of form p k I j (x kj ) only for each pass transistor path which decodes a transition path to a stable state S k under an input I j in which a present state variable y i undergoes a change in value, and wherein a state variable product expression is substituted for each partition p k in the design of each network portion, where each said state variable product expression corresponds to a covering by said each partition p k of only the portion of the transition path to the stable state of said each partition p k which contains an unstable state, wherein each partition p k of the circuit's present state variables under each input variable I j of the flow table is associated with a stable internal state of the circuit, and each said partition p k includes a block corresponding to a transition pair or k-set of said stable internal state, and where the design for each next state variable Y i includes the term p k I j (1) if the block of the partition p k corresponds to a transition path in which present state variable bit y i undergoes a transition from zero to one, where the design for each next state variable Y i includes the term p k I j (0) if the block of the partition p k corresponds to a transition path in which present state variable bit y i undergoes a transition from one to zero.

Claim 36

Dependent Claim 58 words

The circuit of claim 33, wherein the flow table comprises states S i for each input signal I j , where i is a non-negative integer less than or equal to n, and wherein the flow table is encoded with a one-hot-code state assignment with present state variable y i equal to one in state S i .

Claim 37

Dependent Claim 74 words

The circuit of claim 34, wherein the design for each next state variable Y i includes an enable term of form y k I j (1) for each state transition from unstable state S k to state S i under input signal I j , and a disable term y i I k (0) for each state transition from unstable state S p to unstable state S j under input signal I k .

Claim 38

Dependent Claim 29 words

The circuit of claim 34, wherein the circuit is constrained to operate in a non-normal mode in which only one state variable is allowed to change at a time.

Claim 39

Dependent Claim 28 words

The circuit of claim 34, wherein the circuit is constrained to operates in a non-normal mode in which two state variable changes are required for each state transition.

Claim 40

Dependent Claim 110 words

The circuit of claim 37, wherein the design for next state variable Y i includes the enable term y k I j (1) for each internal state S i of the flow table that is stable under input signal I j , and for each state transition from unstable state S k to state S i , and wherein the design for next state variable Y i includes the disable term y i y j (0) for each internal state S j of the flow table that is unstable under input variable I j , and for each state transition from stable state S i to state S j .

Claim 41

Dependent Claim 99 words

The circuit of claim 37, wherein the design for next state variable Y i includes the enable term y k I j (1) for each internal state S i of the flow table that is stable under input variable I j , and for each state transition from unstable state S k to state S i , and wherein the design for next state variable Y i includes the disable term y i y k I m (0) for each state transition from stable state S i to unstable state S k caused by input variable I m .

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1993-03-26	1993-09-25	1994-03-27	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1997-03-26	1997-09-25	1998-03-27	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2001-03-26	2001-09-25	2002-03-27	$7700.00	Window Closed / Lapsed

Method for designing pass transistor asynchronous sequential circuits

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