US4453096A
Expired / Lapsed
US
⏱️ 0.0 years remaining
MOS Transistor type integrated circuit for the execution of logical operations on a plurality of data signals
Assignee: US Philips Corp
•
Filing: 1980-04-01
•
Granted: 1984-06-05
•
Expires: 2000-04-01
Abstract
Abstract Four-pole circuits for iterative modular use in integrated circuits fabricated with complementary MOS (C-MOS) technology or LOCMOS technology, having a high density of circuit elements and high speed obtained at low dissipation. Each of said four-pole circuit modules has two signal inputs, a control input and a signal output line. The four-pole circuit modules may be constructed from two series connected complementary MOS transistors or two series-connected p-MOS transistors. In the latter case the control input must be doubled to receive the control signal and its inverted value. The signal outut is then alternatively connected to one of the two signal inputs (logically or physically) by each of the two values of the control signal. This two-level logic, input signal and control signal, results in circuit modules easily used in computer aided design for multiplexers in which said four-pole circuits are successively arranged in two or more levels, for a BUS-configuration; and can be arranged in series having a common control and different combinations of input signals to form an arithmetic member for one bit in respect of two input quantities. Series of this kind can be combined to form a multi-bit arithmetic member.
Inventors
- 👤 Claude J. P. F. Le Can
- 👤 Karel Hart
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 04:29
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1737; H03K19/20; H03K19/21; H03K19/215
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
379 words
An integrated circuit for the execution of logical operations on at least three data signals, said circuit comprising: at least a first and a second four pole circuit module (121, 123), each module being a series combination of a first and a second MOS-transistor of a single conductivity type between a first end and a second end; each said series combination having a first data input terminal at its first end and a second data input terminal at its second end for receiving respective data signals of a first amplitude range; with each said series combination said first MOS-transistor having a first gate electrode and said second MOS-transistor having a second gate electrode for receiving mutually inverse control signals of a second amplitude range, said second amplitude range encompassing and being larger than said first amplitude range; each said series combination having a first data output terminal situated at the junction of said two MOS-transistors for outputting a data signal of said first amplitude range; wherein a first value of said control signal applied to a series combination renders exclusively a current path between said first data input termial and said first data output terminal conductive, while a second value of said control signal renders exclusively a current path between said second data input terminal and said first data output terminal conductive; wherein the data output terminal of said first four pole circuit module is coupled to a data input terminal of said second four pole circuit module for effecting a two stage logical operation on at least one data signal receivable on at least one of said data input terminals; wherein said integrated circuit furthermore comprises: at least one third data input terminal (109-116) for receiving a data signal to at least one first or second data input terminal of said four pole circuit modules; register means having a fourth data input terminal connected to at least one said first data output terminal for temporarily storing a data signal generated by at least one of said four pole circuit modules; at least two supply terminals (54, 56) for receiving power for powering said register means; and at least one second data output terminal (55, 57) for outputting a data signal receivable from an output of said register means.
Claim 2
Dependent Claim
379 words
An integrated circuit for the execution of logical operations on at least three data signals, said circuit comprising: at least a first and a second four pole circuit module (121, 123), each module being a series combination of a first and a second MOS-transistor of a single conductivity type between a first end and a second end; each said series combination having a first data input terminal at its first end and a second data input terminal at its second end for receiving respective data signals of a first amplitude range; with each said series combination said first MOS-transistor having a first gate electrode and said second MOS-transistor having a second gate electrode for receiving mutually inverse control signals of a second amplitude range, said second amplitude range encompassing and being larger than said first amplitude range; each said series combination having a first data output terminal situated at the junction of said two MOS-transistors for outputting a data signal of said first amplitude range; wherein a first value of said control signal applied to a series combination renders exclusively a current path between said first data input termial and said first data output terminal conductive, while a second value of said control signal renders exclusively a current path between said second data input terminal and said first data output terminal conductive; wherein the data output terminal of said first four pole circuit module is coupled to a data input terminal of said second four pole circuit module for effecting a two stage logical operation on at least one data signal receivable on at least one of said data input terminals; wherein said integrated circuit furthermore comprises: at least one third data input terminal (109-116) for receiving a data signal to at least one first or second data input terminal of said four pole circuit modules; register means having a fourth data input terminal connected to at least one said first data output terminal for temporarily storing a data signal generated by at least one of said four pole circuit modules; at least two supply terminals (54, 56) for receiving power for powering said register means; and at least one second data output terminal (55, 57) for outputting a data signal receivable from an output of said register means.
Claim 3
Dependent Claim
274 words
An integrated circuit as claimed in claim 1, wherein said register means comprises a clock driven hold circuit for storing one data bit, said hold circuit comprising: a third series combination (43, 46), between a third and a fourth end, of two third MOS transistors of mutually opposite conductivity types interconnected by a MOS transistor (45), said third series combination having a second junction; a fourth series combination (47, 50) corresponding to said third series combination between said third and said fourth end, having two fourth MOS transistors interconnected by a MOS transistor (49) and having a third junction; means for powering (37, 39) said third and fourth series combinations by supplying said third and fourth ends with supply voltages having a voltage range which encompasses said second amplitude range; a network for mutually cross-coupling said second junction to the two gate electrodes of said fourth MOS transistors and said third junction to the two gate electrodes of said third MOS transistors; wherein the two further MOS transistors (45, 49) are coupled between the respective second and third junctions and a respective third and fourth MOS transistor, and being of the same conductivity type as the latter, the gate electrodes of said MOS transistors being connected with respective data input terminals of the hold circuit, inputting mutually inverse data input signals while, under control of said clock, simultaneously interrupting at least part of said third and series combinations, the data input signals being receivable on said second and third junctions, and wherein the hold circuit produces output signals (41, 42) on said cross-coupling network having a third amplitude range encompassing said second amplitude range.
Claim 4
Dependent Claim
29 words
An integrated circuit as claimed in claim 1, wherein said MOS-transistors have a common semiconductor body having a silicon substrate layer provided with electrically separating inset silicon oxide regions.
References Cited (Backward Citations)
US3603814A
Cited
US3651342A
Cited
US4049974A
Cited
US3767906A
Cited
US3930169A
Cited
US3965459A
Cited
US4021781A
Cited
US4084105A
Cited
US4006365A
Cited
US4010385A
Cited
US4039858A
Cited
US4064405A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-06-05 | 1987-12-05 | 1988-06-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-06-05 | 1991-12-05 | 1992-06-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-06-05 | 1995-12-05 | 1996-06-05 | $7700.00 | Window Closed / Lapsed |