Precharge arithmetic logic unit

Claim 2

A circuit for determining the parity between a plurality of logic signals comprising: a. first pair of series connected field effect transistors connected between a first node and a first clock voltage source, said transistor having gates for receiving logic signals, and means for applying a first logic signal and the complement of a second logic signal to the gates of the field effect transistors, respectively; b. a second pair of series connected field effect transistors connected between said first node and said first clock source, said second pair of transistors having gates for receiving logic signals, and means for applying the complement of said first logic signal and said second logic signal to the gates of the second pair, respectively; and c. means for precharging said first node to a reference negative voltage simultaneously with applying said first and second signals whereby when said first and second signals are of opposite logic levels said node is discharged thereby producing at said node a logic 1 level corresponding to uneven parity.

Claim 3

A circuit as set forth in claim 1 wherein said means for precharging said first node includes a field effect transistor connected between said node and said reference negative voltage, the gate electrode of said transistor being connected to said first clock voltage source.

Claim 4

A circuit for determining the parity between a plurality of logic signals comprising: a. first pair of series connected field effect transistors connected between a first node and a first clock voltage source, said transistors respectively having gates for receiving a first logic signal and the complement of a second logic signal; b. a second pair of series connected field effect transistors connected between said first node and said first clock source, said second pair of transistors respectively having gates for receiving the complement of said first logic signal and said second logic signal; c. means for precharging said first node to a reference negative voltage simultaneously with applying said first and second signals whereby when said first and second signals are of opposite logic levels said node is discharged, thereby producing at said node a logic 1 level corresponding to uneven parity, said means for precharging said first node including a field effect transistor connected between said node and said reference negative voltage, the gate electrode of said transistor being connected to said first clock voltage source; d. a third pair of series connected field effect transistors connected between a second node and said first clock source, respectively having gates for receiving said first and second logic signals; e. fourth pair of series connected field effect transistors connected between said second node and said first clock source, respectively having gates for receiving the complement of said first and second logic signals; and f. means for precharging said second node to a reference negative voltage simultaneously with applying said first and second signals whereby when said first and second signals are of like logic levels said second node is discharged producing at said second node a logic 1 level corresponding to even parity.

Claim 5

A circuit for determining the parity between a plurality of logic signals comprising: a. first pair of series connected field effect transistors connected between a first node and a first clock voltage source, said transistors respectively having gates for receiving a first logic signal and the complement of a second logic signal; b. a second pair of series connected field effect transistors connected between said first node and said first clock source, said second pair of transistors respectively having gates for receiving the complement of said first logic signal and said second logic signal; c. means for precharging said first node to a reference negative voltage simultaneously with applying said first and second signals whereby when said first and second signals are of opposite logic levels said node is discharged, thereby producing at said node a logic 1 level corresponding to uneven parity, said means for precharging said first node including a field effect transistor connected between said node and said reference negative voltage, the gate electrode of said transistor being connected to said first clock voltage source; d. a third pair of series connected field effect transistors connected between a second node and said first clock source, respectively having gates for receiving said first and second logic signals; e. fourth pair of series connected field effect transistors connected between said second node and said first clock source, respectively having gates for receiving the complement of said first and second logic signals; and f. means for precharging said second node to a reference negative voltage simultaneously with applying said first and second signals whereby when said first and second signals are of like logic levels said second node is discharged producing at said second node a logic 1 level corresponding to even parity.

Claim 6

A parity circuit as set forth in claim 3 wherein said means for precharging said second node includes a second insulated-gate-field-effect-transistor connected between said second node and said reference voltage source, said second transistor having a gate connected to said clock source.

Claim 7

A parity circuit as set forth in claim 4 including: a. fifth and sixth field effect transistors commonly connected at one electrode to said first node and respectively being connected at the other electrode to third and fourth nodes, said fifth and sixth transistors respectively having gates for receiving a third input signal and the complement of said third signal; and b. seventh and eighth field effect transistors commonly connected at one electrode to said second node and respectively being connected at the other electrode to said third and fourth nodes, said seventh and eighth transistors respectively having gates for receiving the complement of said third signal and said third signal; and c. means for precharging said third and fourth nodes to a reference negative voltage simultaneously with application of said third signal whereby either said third node or said fourth node will be selectively discharged in response to the logic level of said third signal said discharged node respectively corresponding to uneven parity and even parity.

Claim 8

A parity circuit as set forth in claim 5 wherein said means for precharging said third and fourth nodes comprises a field effect transistor connected between each node and said negative reference voltage, having a gate for receiving said first clock signal.