US3619646A
Expired / Lapsed
US
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Frequency divider circuit
Assignee: Centre Electronique Horloger SA
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Filing: 1969-11-12
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Granted: 1971-11-09
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Expires: 1989-11-12
Abstract
Abstract A frequency divider circuit including at least one logical structure complying with the Boole Relations: A BI1+AI2 and B BI1+AI2 in which I1 and I2 are two complementary input quantities and A and B two output quantities. The logical structure comprises three pairs of field effect transistors, such as MOS-transistors having isolated gates. A cascade of binary frequency divider circuits can be made as an integrated circuit.
Inventors
- 👤 Eric Andre Vittoz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:57
CPC Classifications
G; G04; G04G; G04G3/00; G04G3/02; H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
189 words
A frequency divider circuit comprising at least one logical structure complying with the Boole relations: A BI1+AI2 and B BI1+AI2 in which I1 and I2 are two complementary input quantities, and A and B are two output quantities, said logical structure comprising first, second and third pairs of field-effect transistors, each of the transistors in said pairs having a source, a drain and a gate, the sources of one transistor of the first and one transistor of the second pair being connected together to the drain of one transistor of the third pair, and the sources of the two other transistors of the first and second pairs being connected to the drain of the other transistor of the third pair, the two sources of the transistors of the third pair being connected together to a terminal of a voltage source, the two drains of the transistor of the first pair being connected together and the two drains of the transistor of the second pair being connected together respectively, the outputs of said frequency divider circuit apPearing at the drains of the transistors of said first and second pairs respectively.
Claim 2
Dependent Claim
189 words
A frequency divider circuit comprising at least one logical structure complying with the Boole relations: A BI1+AI2 and B BI1+AI2 in which I1 and I2 are two complementary input quantities, and A and B are two output quantities, said logical structure comprising first, second and third pairs of field-effect transistors, each of the transistors in said pairs having a source, a drain and a gate, the sources of one transistor of the first and one transistor of the second pair being connected together to the drain of one transistor of the third pair, and the sources of the two other transistors of the first and second pairs being connected to the drain of the other transistor of the third pair, the two sources of the transistors of the third pair being connected together to a terminal of a voltage source, the two drains of the transistor of the first pair being connected together and the two drains of the transistor of the second pair being connected together respectively, the outputs of said frequency divider circuit apPearing at the drains of the transistors of said first and second pairs respectively.
Claim 3
Dependent Claim
50 words
A frequency divider circuit according to claim 1 further comprising first and second load resistors, each having one end coupled respectively to the drain of a transistor of said first and second pairs, the other ends of said load resistors being coupled to the other terminal of said voltage source.
Claim 4
Dependent Claim
60 words
A frequency divider circuit according to claim 1 further comprising a fourth pair of field-effect transistors, each transistor having one electrode coupled respectively to the drain of a transistor of said first and of said second pairs of field-effect transistors, the second electrodes of said fourth pair of field-effect transistor being coupled to the other terminal of said voltage source.
Claim 5
Dependent Claim
26 words
A frequency divider circuit according to claim 1, comprising two logical structures having common outputs, the transistors of the two logical structures being of inverse type.
Claim 6
Dependent Claim
61 words
A frequency divider circuit according to claim 4, including several binary stages with two logical structures each, in integrated form in a common substrate, the N-type transistor structures of all the stages being formed in a same P-type region of this substrate, and the P-type transistor structures of all the stages being formed in a same N-type region of this substrate.
Claim 7
Dependent Claim
156 words
A frequency divider circuit comprising at least one logical structure complying with the Boole relations: A BI1+AI2 and B BI1+AI2 in which I1 and I2 are two complementary input quantities, and A and B are two output quantities, said logical structure comprising first, second and third pairs of field-effect transistors, each of the transistors in said pairs having a source, a drain and a gate, the four sources of the transistors of the two first pairs being connected together to the two drains of the third pair, the two sources of the transistors of the third pair being connected together to a terminal of a voltage source, the two drains of the transistor of the first pair being connected together and the two drains of the transistor of the second pair being connected together respectively, the outputs of said frequency divider circuit appearing at the drains of the transistors of said first and second pairs, respectively.
Claim 8
Dependent Claim
156 words
A frequency divider circuit comprising at least one logical structure complying with the Boole relations: A BI1+AI2 and B BI1+AI2 in which I1 and I2 are two complementary input quantities, and A and B are two output quantities, said logical structure comprising first, second and third pairs of field-effect transistors, each of the transistors in said pairs having a source, a drain and a gate, the four sources of the transistors of the two first pairs being connected together to the two drains of the third pair, the two sources of the transistors of the third pair being connected together to a terminal of a voltage source, the two drains of the transistor of the first pair being connected together and the two drains of the transistor of the second pair being connected together respectively, the outputs of said frequency divider circuit appearing at the drains of the transistors of said first and second pairs, respectively.
Claim 9
Dependent Claim
49 words
A frequency divider circuit according to claim 6 further comprising first and second load resistors, each having one end coupled respectively to the drain of a transistor of said first and second pairs, the other ends of said resistors being coupled to the other terminal of said voltage source.
Claim 10
Dependent Claim
60 words
A frequency divider circuit according to claim 6 further comprising a fourth pair of field-effect transistors, each transistor having one electrode coupled respectively to the drain of a transistor of said first and of said second pairs of field-effect transistors, the second electrodes of said fourth pair of field-effect transistor being coupled to the other terminal of said voltage source.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-08 | 1975-05-10 | 1975-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-08 | 1979-05-10 | 1979-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-08 | 1983-05-10 | 1983-11-09 | $7700.00 | Window Closed / Lapsed |