US3649844A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Parity circuit in ecl technique with short transit time
Assignee: Siemens AG
•
Filing: 1970-06-01
•
Granted: 1972-03-14
•
Expires: 1990-06-01
Abstract
Abstract A three-input parity circuit constructed in accordance with ECL techniques employs four current switches each having s pair of transistors, and wherein a pair of collector load resistors are shared by three of the switches and shared via one of those three switches by the fourth current switch to obtain, in response to three input signals, formation of the logical function (or its inverse) of P a.b.c+ a.b.c+a.b.c+a.b.c.
Inventors
- 👤 Friedrich-Karl Kroos
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 10:58
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/086; H03K19/0866
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
260 words
A parity circuit constructed in ECL technique and having a short transit time, comprising: three current switches each of which includes first and second transistors, each of said transistors having a base, an emitter and a collector and the transistors of each said switch being emitter coupled, said bases of each said first transistor adapted to receive respective input signals and said bases of each of said second transistors adapted for connection to a fixed potential, said coLlectors divided into two groups and the collectors so associated connected together to form first and second gating points; a first diode connected to said first gating point and adapted for connection to a reference potential and poled in its pass direction, and a first resistor connected in parallel with said first diode, a second diode connected to said second gating point and adapted for connection to the reference potential and poled in its pass direction, and a second resistor connected in parallel with said second diode; a fourth current switch adapted to receive an input signal and including first and second current paths, said emitters of said first current switch connected to said first current path of said fourth current switch, and said emitters of said second current switch connected to said second current path of said fourth current switch; means for providing constant currents connected to said emitters of said third current switch and to said first and second current paths of said fourth current switch; and means connected to said first and second gating points for deriving an output signal.
Claim 2
Dependent Claim
260 words
A parity circuit constructed in ECL technique and having a short transit time, comprising: three current switches each of which includes first and second transistors, each of said transistors having a base, an emitter and a collector and the transistors of each said switch being emitter coupled, said bases of each said first transistor adapted to receive respective input signals and said bases of each of said second transistors adapted for connection to a fixed potential, said coLlectors divided into two groups and the collectors so associated connected together to form first and second gating points; a first diode connected to said first gating point and adapted for connection to a reference potential and poled in its pass direction, and a first resistor connected in parallel with said first diode, a second diode connected to said second gating point and adapted for connection to the reference potential and poled in its pass direction, and a second resistor connected in parallel with said second diode; a fourth current switch adapted to receive an input signal and including first and second current paths, said emitters of said first current switch connected to said first current path of said fourth current switch, and said emitters of said second current switch connected to said second current path of said fourth current switch; means for providing constant currents connected to said emitters of said third current switch and to said first and second current paths of said fourth current switch; and means connected to said first and second gating points for deriving an output signal.
Claim 3
Dependent Claim
128 words
A parity circuit as set forth in claim 1, for the formation of the logical function P a.b.c + a.b.c + a.b.c + a.b.c where a, a are the input signal possibilities to said first and second current switches b, b are the input signal possibilities to said fourth current switch and c, c are the input signal possibilities for said third current switch, wherein said collectors of said second transistors of said first and third current switches and of said first transistor of said second current switch are connected to said first gating point, and said collectors of said first transistors of said first and third current switches and said collector of said second transistor of said second current switch are connected to said second gating point.
Claim 4
Dependent Claim
129 words
A parity circuit as set forth in claim 1, for the formation of the logical function Q P a.b.c + a.b.c + a.b.c + a.b.c where a, a are the input signal possibilities to said first and second current switches, b, b are the input signal possibilities to said fourth current switch, and c , c are the input signal possibilities to said third current switch, and wherein said collection of said second transistor of said first current switch and of said first transistors of said second and third current switches are connected to said first gating point, and said collectors of said second transistors of said second and third current switches and of said first transistor of said first current switch are connected to said second gating point.
Claim 5
Dependent Claim
91 words
A parity circuit as set forth in claim 1, wherein said means for deriving an output signal comprises a resistor, first and second transistors each having a base, an emitter and a collector, said bases individually connected to said first and second gating points, said collectors connected together and adapted for connection to the reference potential, and said emitters connected together and connected to and adapted for connection to another reference potential by way of said resistor, and an output terminal connected to the junction of said emitters and said resistor.
Claim 6
Dependent Claim
128 words
A parity circuit as set forth in claim 1, wherein said first current path includes a first transistor having a collector connected to said emitters of said first current switch, an emitter connected to said means for providing constant currents, and a base, and said second current path includes a second transistor having a collector connected to said emitters of said second current switch, an emitter connected to said means for providing constant currents, and a base connected to a reference potential, and further comprising a resistor-transistor network, inclUding a base-emitter diode, connected to said base and adapted to receive the input signal of said fourth current switch for shifting the potential at said base by at least the voltage of said base-emitter diode in a conductive state.
Claim 7
Dependent Claim
36 words
A parity circuit as set forth in claim 5, wherein said means for providing constant currents comprises a resistor connected to said emitters of said third current switch and adapted for connection to another reference potential.
Claim 8
Dependent Claim
59 words
A parity circuit as set forth in claim 5, wherein said means for providing constant currents comprises a resistor, and a transistor having an emitter connected to and adapted for connection to another reference potential via said resistor, a base adapted for connection to another fixed potential and a collector connected to said emitters of said fourth current switch.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-03-14 | 1975-09-13 | 1976-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-03-14 | 1979-09-13 | 1980-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-03-14 | 1983-09-13 | 1984-03-14 | $7700.00 | Window Closed / Lapsed |