US3767906A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multifunction full adder
Assignee: RCA Corp
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Filing: 1972-01-21
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Granted: 1973-10-23
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Expires: 1992-01-21
Abstract
Abstract An arithmetic unit which may be utilized in any binary computational circuit. The arithmetic unit utilizes a pair of exclusive OR gates connected in series. One of the exclusive OR gates operates upon input signals (e.g. addend and augend) to produce an output signal. The other exclusive OR gate operates upon input signals (e.g. carry and output from the first OR gate) to produce the sum output signal. A two-way transmission gate switch operates upon certain input signals (e.g. carry, addend or augend, and output signal produced by the first exclusive OR gate) to produce the carry output signal.
Inventors
- 👤 R Pryor
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 12:47
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/501; G06F7/503
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
190 words
In combination: binary full-adder circuit means having a first exclusive OR gate with first and second input terminals adapted to receive first and second binary signals, respectively, and producing the logical exclusive OR function thereof at a first output terminal, said circuit means having a second exclusive OR gate for receiving the output from said first output terminal and a carry-in binary signal and producing the logical exclusive OR function thereof at a second output terminal representative of the arithmetic sum of said first, second and carry-in binary signals, said circuit means including means coupled to said first and second exclusive OR gates for producing a signal representative of the arithmetic carry of the input signals; and switch means having a pair of input terminals, a control terminal and an output terminal, one switch means input terminal adapted to receive a source of reference potential, the other switch means input terminal connected to one input terminal of said first exclusive OR gate, and the switch means control terminal connected to said first output terminal for selectively connecting one of the switch means input terminals to the switch means output terminal.
Claim 2
Dependent Claim
190 words
In combination: binary full-adder circuit means having a first exclusive OR gate with first and second input terminals adapted to receive first and second binary signals, respectively, and producing the logical exclusive OR function thereof at a first output terminal, said circuit means having a second exclusive OR gate for receiving the output from said first output terminal and a carry-in binary signal and producing the logical exclusive OR function thereof at a second output terminal representative of the arithmetic sum of said first, second and carry-in binary signals, said circuit means including means coupled to said first and second exclusive OR gates for producing a signal representative of the arithmetic carry of the input signals; and switch means having a pair of input terminals, a control terminal and an output terminal, one switch means input terminal adapted to receive a source of reference potential, the other switch means input terminal connected to one input terminal of said first exclusive OR gate, and the switch means control terminal connected to said first output terminal for selectively connecting one of the switch means input terminals to the switch means output terminal.
Claim 3
Dependent Claim
106 words
The combination recited in claim 1 wherein said switch means comprises: two pairs of complementary transistors, each transistor having a conduction path and a second electrode for controlling the conduction of the path, each pair of said complementary transistors coupled between a separate one of said pair of input terminals of said switch means and said switch means output terminal; and means coupling said control electrodes to said switch means control terminal for turning both transistors of one pair of complementary transistors on while maintaining both transistors of the other pair of complementary transistors off in response to signals present on said switch means control terminal.
Claim 4
Dependent Claim
84 words
The combination recited in claim 1 further comprising a three-input switch means, each input being coupled to a separate one of the output terminals of said first exclusive OR gate, said second exclusive OR gate and said switch means, said three-input switch means having an output terminal and a plurality of control terminals whereby signals applied to the three inputs are selectively conducted to said output terminal of said three input switch means in response to signals applied to said plurality of control terminals.
Claim 5
Dependent Claim
100 words
The combination recited in claim 1 further comprising a second switch means having a pair of input terminals, a control terminal and an output terminal, each input terminal adapted to receive a separate source of reference potential, the output terminal coupled to one of the input terminals of said first exclusive-OR gate and the control terminal adapted to receive a source of binary signals so that signals applied to the input terminals are selectively conducted to said output terminal of said second switch means in response to said binary signals applied to the control terminal of said second switch means.
References Cited (Backward Citations)
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US3612847A
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US3388239A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-22 | 1977-04-23 | 1977-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-22 | 1981-04-23 | 1981-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-22 | 1985-04-23 | 1985-10-23 | $7700.00 | Window Closed / Lapsed |