Modular unit for digital arithmetic systems

Claim 2

A modular circuit unit having four inputs X, Y, Z and c and corresponding negated inputs X, Y, Z and c, and having four outputs, R, S, T and C and corresponding negated outputs R, S, T and C, said unit comprising five identical logic elements each having four inputs e, f, g and h and two outputs s and s, where s is the negated value of s, each said logic element constituting means for producing the following relationships: s (e f)(g h) s (ef) (gh), said logic elements being connected to each other and to said inputs X, Y, Z and c and said outputs R, S, T and C, as well as to negated inputs X, Y, Z and c and negated outputs R, S, T and C, in the following manner, wherein each subscript represents a respective logic element:

Claim 3

An arrangement as defined in claim 1 further comprising at least one input unit constituted by a logic element identical with each of said logic elements, said input unit having two outputs s and s which present one of the sets of inputs X, X or Y, Y or Z, Z, said input unit further having a first pair of inputs e and h and a second pair of inputs f and g, said input e being connected to receive a binary information bit, said input h being connected to receive the negated value of such binary information bit, and said inputs f and g being connected to receive binary control signals whose values cause each of said outputs to present such binary information bit in direct or negated form or to present a binary value which is independent of the binary information bit.

Claim 4

An arrangement as defined in claim 1 further comprising at least one input unit having a signal input, a control input, and a signal output connected to provide one of said inputs X, Y and Z, said input unit being arranged to deliver to its said output either the binary signal appearing at its said signal input, directly or in negated form, or a binary ''''1'''' or ''''0,'''' independent of the signal appearing at its said signal input, under the control of the signal applied to its said control input.

Claim 5

An arrangement as defined in claim 3 connected to act as an arithmetic circuit for the ith bit location of an n-bit arithmetic unit.

Claim 6

An arrangement as defined in claim 4 wherein there are n of said arithmetic circuits, the ith one of said circuits being associated with a respective ith bit location of said arithmetic unit.

Claim 7

An arrangement as defined in claim 5 wherein said arithmetic unit further comprises operand storage registers D, A, B, U and V each having n+1 bit locations, and each said logic unit is provided with three input units each connected to provide a respective one of said inputs X, Y and Z, the signal inputs to said input units being designated X'', y'' and z'', respectively, and wherein, for the ith arithmetic circuit: said signal input X'' is connected to the ith bit location output of said storage register D; said signal input Y'' is connected to the ith bit location output of said register A; said signal input Z'' is connected to the ith bit location output of said register U; said input c is connected to the output C of that one of said circuits provided for the next lower bit location (i-1) of said arithmetic unit; said output R is connectable to the (i-1) th bit location input of said register B; said output S is connectable to the ith bit location input of said register B; and said output T is connectable to the ith bit location input of said register V.

Claim 8

An arrangement as defined in claim 6 further comprising, in order to eliminate the need for transferring stored values from one of said registers to another during multistep arithmetic operations, switching means connected between said registers A, B, U and V and each said arithmetic circuit, said switching means being arranged for alternately connecting: said output R of said ith arithmetic circuit to the (i-1)th bit location input of either said register B or said register A; said output T or said ith arithmetic circuit to the ith bit location input of either said register V or said register U; the Y'' input of said ith arithmetic circuit to the ith bit location output of either said register A or said register B; and the input Z'' of said ith arithmetic circuit to the ith bit location of either said register U or said register V; and wherein said switching means are controlled for causing each said register to be connected only to inputs or to outputs of said arithmetic circuits at any given time.