Cmos odd multiple repetition rate divider circuit

Claim 1

An odd-multiple divider circuit employing flip-flops and having a minimum number of circuit components each flip-flop including a master and a slave section, each master and each slave section being comprised of a first and a second Complementary-Metal-Oxide-Semiconductor-Field-Effect-Transistor (CMOSFET) transmission gate and a pair of series connected CMOSFET inverters, the first CMOSFET transmission gate of each master and slave section having an output terminal connected to the input terminal of the pair of series connected CMOSFET inverters thereof, the second CMOSFET transmission gate of each master and slave section providing a feedback path from the output terminal of the pair of series connected CMOSFET inverters to the input terminal of the pair of series connected CMOSFET inverters, the output terminal of the series connected CMOSFET inverters of each master section of each flip-flop being connected to the input terminal of the first CMOSFET transmission gate of each slave section of the flip-flop, each of the CMOSFET transmission gates of each master and slave section having control terminals adapted to receive a clock signal having a pair of periodic and complementary binary signals, the divider circuit including in combination: a first one of the flip-flops having an input terminals and a single output terminal, said input terminal being connected to the input terminal of the first CMOSFET transmission gate of the master section of said first flip-flop, said single output terminal being connected to the output terminal of the pair of series connected CMOSFET inverters of the slave section of said first flip-flop; a second one of the flip-flops having an input terminal and first and second output terminals, said input terminal being connected to the input of the first CMOSFET transmission gate of the master section of said second flip-flop, said input terminal also being connected to said single output terminal of said first flip-flop, said first output terminal being connected to the output terminal of the pair of series connected CMOSFET inverters of the master section of said second flip-flop, said second output terminal being connected to the output terminal of the pair of series connected CMOSFET inverters of the slave section of said second flip-flop; the operation of said first and second flip-flops thereby being continuously dependent on each cycle of the clock signal to transfer the logic state at the input terminals thereof to the output terminals thereof regardless oF the logic state at the input terminals thereof; gate means having first, second and third input terminals and an output terminal, said first input terminal being connected to said output terminal of said first flip-flop, said second input terminal being connected to said second output terminal of said second flip-flop; first circuit means coupling said output terminal of said gate means to said input terminal of said first flip-flop; and second circuit means coupling said first output terminal of said second flip-flop to said third input terminal of said gate means for rendering the divider circuit suitable to divide the frequency of the clock signal by an odd-multiple integer, the odd-multiple divider circuit having a minimum number of circuit components.