Quinary reduction stage and forward-reverse counter

Claim 2

Quinary reduction stage, comprising, in combination, twophase signal generator means furnishing a primary combination signal comprising a first and second binary signal sequence having a predetermined period, said second binary signal sequence having a predetermined phase shift relative to said first binary signal sequence, at a first and second signal generator output respectively; a first and second output line; and a plurality of direct current coupled logic circuits including means for connecting said first and second signal generator outputs with said first and second output lines for generating a secondary combination signal on said output lines, said secondary combination signal comprising a first and second binary signal sequence having a phase shift corresponding to said predetermined phase shift, but having a secondary period which is five times said predetermined period.

Claim 3

Quinary reduction stage as set forth in claim 1, wherein said two-phase signal generator means further comprise a third and fourth signal generator output furnishing, respectively, the inverse of said first and second binary signal sequence of said primary combination signal; a third and fourth output line furnishing, respectively, the inverse of the first and second binary signal sequence of said secondary combination signal; and wherein said plurality of logic circuits comprise a first and second primary circuit channel furnishing, respectively, said first and second binary signal sequence of said secondary combination signal, and a third, fourth and fifth primary circuit channel including means for furnishing, respectively, a first primary auxiliary signal, a second primary auxiliary signal, and a third primary auxiliary signal.

Claim 4

Quinary reduction stage as set forth in claim 2, also comprising at least a first, second, third, and fourth secondary circuit channel, each channel including means for logically interconnecting the corresponding primary circuit channel and at least one other of said circuit channels, such that each of said secondary circuit channels furnishes a secondary channel output signal which is the inverse of the signal furnished by the corresponding primary circuit channel, each pair of corresponding primary and secondary channels thus constituting a flip-flop.

Claim 5

Quinary reduction stage as set forth in claim 3, wherein said primary and secondary circuit channels are interconnected and connected to said input lines and to said output lines such as to satisfy simultaneously the following Boolean equations:

Claim 6

Quinary reduction stage as set forth in claim 2, wherein all of said primary circuit channels are identical; also comprising first, second, third and fourth mutually identical auxiliary logic means, interconnected between said signal generator output and said primary circuit channels and including means for furnishing auxiliary input signals to said primary circuit channels as a function of combinations of conditions on said input lines.

Claim 7

Quinary reduction stage as set forth in claim 5, wherein said identical auxiliary logic means each comprise an AND gate, each of said AND gates having two inputs, each of said inputs being connected to said signal generator outputs such that said auxiliary input signals each correspond to one of the four possible condition combinations at said signal generator outputs.

Claim 8

Quinary reduction stage as set forth in claim 6, also comprising first, second, third, fourth and fifth secondary circuit channels, each identical to the corresponding primary circuit channel, each interconnected to said auxiliary logic means, said primary circuit channels and said output lines with direct current coupling, such that each secondary circuit channel furnishes a secondary circuit channel output signal which is the inverse of the corresponding primary circuit channel output signal.

Claim 9

Quinary reduction stage as set forth in claim 7, wherein each of said circuit channels comprises two channel AND gates; an OR gate series connected to said two channel AND gates; and an inverter gate series connected to said OR gate.

Claim 10

Quinary reduction stage as set forth in claim 7, wherein said auxiliary logic means outputs are designated N'', O'', P'' and Q''; and wherein said auxiliary logic means simultaneously satisfy the following Boolean equations: N'' X Y P'' X Y O'' X Y Q'' X Y wherein each of said primary circuit channels has a corresponding secondary circuit channel, identical to it, connected to it such that said primary circuit channels and secondary circuit channels simultaneously satisfy the following Boolean equations: A BN'' +EO''+a a bP''+eQ''+A B CN''+AO''+b b cP''+aQ''+B C DN''+BO''+c c dP''+bQ''+C D EN''+CO''+d d eP''+cQ''+D E AN''+DO''+e e aP'' dQ''+D wherein A,a A; C,c C constitute the first and second phase of said secondary combination signal respectively, while B, D, and E constitute auxiliary signals.

Claim 11

Quinary reduction stage as set forth in claim 1, wherein said logic circuits comprise hydraulic elements.

Claim 12

A forward-reverse counter, comprising, in combination, means for furnishing a two-phase binary signal sequence having a predetermined phase shift between said two phases; and a plurality of direct current coupled reduction stages connected in cascade to said means for furnishing a two-phase binary signal sequence, each of said reduction stages including means for furnishing, in response to an input two-phase binary signal sequence, an output binary signal sequence having the same phase shift as said input binary signal sequence but a period which is an integral multiple of the period of said input two-phase binary signal sequence, at least one of said direct current coupled reduction stages being a quinary reduction stage.

Claim 13

A forward-reverse counter, comprising, in combination, means for furnishing a two-phase binary signal sequence having a predetermined phase shift between said two phases; and a plurality of direct current coupled reduction stages connected in cascade to said means for furnishing a two-phase binary signal sequence, each of said reduction stages including means for furnishing, in response to an input two-phase binary signal sequence, an output binary signal sequence having the same phase shift as said input binary signal sequence but a period which is an integral multiple of the period of said input two-phase binary signal sequence, at least one of said direct current coupled reduction stages being a quinary reduction stage.

Claim 14

A forward-reverse counter as set forth in claim 11, further comprising a direct current coupled binary reduction stage connected in cascade with said direct current coupled quinary reduction stage, thereby forming a decade reduction stage.

Claim 15

A forward-reverse counter for use with multiphase binary signal generator means which, for a continuous change of a physical quantity, generate a primary combination signal consisting of a first predetermined cyclic sequence of possible signal combinations in a plurality of phases for a positive unit change of said quantity and a second sequence for a negative unit change of said physical quantity, each individual change of signal combinations signifying a change of said quantity corresponding to a fraction of said unit change, comprising, in combination, a plurality of input lines, corresponding in number to the number of phases of said primary combination signal, connected to the output of said binary signal generator means; a plurality of output lines corresponding in number to the number of said input lines; a direct current coupled reduction stage interconnecting said input lines and said output lines and including means for generating a secondary combination signal on said output lines having the same sequence of possible signal combinations as said primary combination signal, but having a secondary period which is an integral multiple of the period of said primary combination signal; first counting means having inputs connected to said input lines for counting said individual changes of signal combinations in said primary combination signal and furnishing a first counting signal in response thereto; and second counting means having inputs connected to said output lines for counting a predetermined fraction of individual changes of signal combinations in said secondary combination signal, whereby the ratio of said second counting signal to said first counting signal corresponds to said integral multiple divided by said predetermined fraction.

Claim 16

A forward-reverse counter for use with multiphase binary signal generator means which, for a continuous change of a physical quantity, generate a primary combination signal consisting of a first predetermined cyclic sequence of possible signal combinations in a plurality of phases for a positive unit change of said quantity and a second sequence for a negative unit change of said physical quantity, each individual change of signal combinations signifying a change of said quantity corresponding to a fraction of said unit change, comprising, in combination, a plurality of input lines, corresponding in number to the number of phases of said primary combination signal, connected to the output of said binary signal generator means; a plurality of output lines corresponding in number to the number of said input lines; a direct current coupled reduction stage interconnecting said input lines and said output lines and including means for generating a secondary combination signal on said output lines having the same sequence of possible signal combinations as said primary combination signal, but having a secondary period which is an integral multiple of the period of said primary combination signal; first counting means having inputs connected to said input lines for counting said individual changes of signal combinations in said primary combination signal and furnishing a first counting signal in response thereto; and second counting means having inputs connected to said output lines for counting a predetermined fraction of individual changes of signal combinations in said secondary combination signal, whereby the ratio of said second counting signal to said first counting signal corresponds to said integral multiple divided by said predetermined fraction.

Claim 17

A forward-reverse counter as set forth in claim 13, wherein said direct current coupled reduction stage is a quinary reduction stage; wherein said plurality of phases comprises two phases; wherein said first predetermined cyclic sequence of possible signal combinations in said two phases comprises a sequence of four possible signal combinations; wherein said first counting means count each of said four signal combinations in each period of said primary combination signal; wherein said second counting means count alternate ones of said individual changes of signal combinations in said secondary combination signal, whereby a count on said second countiNg means represents 10 counts in said first counting means.