US4675556A
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Binomially-encoded finite state machine
Assignee: Intel Corp
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Filing: 1986-06-09
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Granted: 1987-06-23
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Expires: 2006-06-09
Abstract
Abstract A finite state machine suitable for MOS fabrication is described. The finite state machine includes a programmed logic array (PLA). The PLA AND plane includes logical inputs and state signal inputs. The state signal inputs are decoded binomially. The state signals are used to activate the AND plane loads, thereby avoiding the necessity of using either a constantly active pull-up or precharge/selective discharge circuitry technique.
Inventors
- 👤 Mel Bazes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:56
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/045
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
114 words
A finite state machine (FSM) circuit which includes a programmed logic array (PLA), comprising: a plurality of first lines for receiving inputs to said PLA; a plurality of second lines intersecting said first lines; logic performing means for selectively coupling ones of said first lines with ones of said second lines; a plurality of switchable loads coupled to said second lines for selectively enabling operation of said logic performing means; and a decoding means for receiving and decoding state outputs of the FSM and for selectively activating certain of said switchable loads as a function of said decoded FSM outputs, said decoding means coupled to said switchable loads, whereby an improved FSM is realized.
Claim 2
Dependent Claim
114 words
A finite state machine (FSM) circuit which includes a programmed logic array (PLA), comprising: a plurality of first lines for receiving inputs to said PLA; a plurality of second lines intersecting said first lines; logic performing means for selectively coupling ones of said first lines with ones of said second lines; a plurality of switchable loads coupled to said second lines for selectively enabling operation of said logic performing means; and a decoding means for receiving and decoding state outputs of the FSM and for selectively activating certain of said switchable loads as a function of said decoded FSM outputs, said decoding means coupled to said switchable loads, whereby an improved FSM is realized.
Claim 3
Dependent Claim
65 words
The circuit of claim 1 wherein the decoding means operates in accordance with a binomial decoding algorithm having a number c of terms, each term uniquely representative of each of said FSM state outputs, each term comprised of a fixed number n of bits, in which the number of said bits which are logic ones is a constant number k for each of said terms.
Claim 4
Dependent Claim
15 words
The circuit of claim 2 wherein the number c of terms is given by ##EQU2##
Claim 5
Dependent Claim
29 words
The circuit of claim 2 wherein each of said plurality of switchable loads comprises a respective plurality of load transistors coupled in series to each of said second lines.
Claim 6
Dependent Claim
32 words
The circuit of claim 1 wherein said logic performing means performs the logical AND function, whereby each of said second lines represents the logical AND of said ones of said first lines.
Claim 7
Dependent Claim
35 words
The circuit of claim 4 wherein the number of said load transistors coupled in series to each of said second lines is equal to the number k of logic ones required by the binomial scheme.
Claim 8
Dependent Claim
49 words
The circuit of claim 6 further comprising a plurality of third lines selectively coupled to ones of said second lines such that each of said third lines represents the logical OR of said ones of said second lines, whereby said third lines provide said state outputs of the FSM.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-06-22 | 1990-12-22 | 1991-06-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-06-22 | 1994-12-22 | 1995-06-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-06-22 | 1998-12-22 | 1999-06-23 | $7700.00 | Window Closed / Lapsed |