US7379316B2 Expired / Lapsed US ⏱️ 0.0 years remaining

Methods and apparatus of stacking DRAMs

Assignee: Google LLC

•

Filing: 2006-09-01

•

Granted: 2008-05-27

•

Expires: 2026-09-01

📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.

Inventors

👤 Suresh N. Rajan

Bibliographic Details

Application Number —

Jurisdiction US

Data Source google_patents

Last Synchronized 2026-11-09 11:14

CPC Classifications

G; G11; G11C; G11C7/00; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C5/00; G11C5/06; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4093; G11C29/00; G11C29/70; G11C29/78; G11C29/80; G11C29/812; G11C5/02; G11C7/10; H; H10; H10W; H10W70/00; H10W70/60

Claims Analysis

Total Claims: 32

Claim 1

Independent Claim 118 words

A memory device for electrical connection to a memory bus, the memory device comprising: a plurality of dynamic random access memory (“DRAM”) integrated circuits, stacked in a vertical direction, each DRAM integrated circuit comprising a memory core of a plurality of cells and accessible at a first speed; and an interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed; wherein the interface integrated circuit is adapted for providing a predetermined electrical load on the memory bus independent of a number of the DRAM integrated circuits to which the interface integrated circuit is electrically coupled.

Claim 2

Dependent Claim 118 words

Claim 3

Dependent Claim 21 words

The memory device as set forth in claim 1 , wherein: each DRAM integrated circuit comprises a DRAM integrated circuit die.

Claim 4

Dependent Claim 23 words

The memory device as set forth in claim 1 , wherein: the plurality of DRAM integrated circuits comprises a DRAM integrated circuit package.

Claim 5

Dependent Claim 26 words

The memory device as set forth in claim 1 , wherein: the interface integrated circuit is adapted to operate in accordance with an industry defined specification.

Claim 6

Dependent Claim 26 words

The memory device as set forth in claim 1 , wherein: the interface integrated circuit is adapted to operate in accordance with a DDR2 SRAM specification.

Claim 7

Dependent Claim 115 words

A memory device for electrical connection to a memory bus, the memory device comprising: a plurality of dynamic random access memory (“DRAM”) integrated circuits, stacked in a vertical direction, each DRAM integrated circuit comprisina a memory core of a plurality of cells and accessible at a first speed; and an interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed; wherein the plurality of DRAM integrated circuits comprise: a working pool of “p” DRAM integrated circuits; and a spare pool of “q” DRAM integrated circuits; wherein “p” and “q” comprise integer values.

Claim 8

Dependent Claim 115 words

A memory device for electrical connection to a memory bus, the memory device comprising: a plurality of dynamic random access memory (“DRAM”) integrated circuits, stacked in a vertical direction, each DRAM integrated circuit comprisina a memory core of a plurality of cells and accessible at a first speed; and an interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed; wherein the plurality of DRAM integrated circuits comprise: a working pool of “p” DRAM integrated circuits; and a spare pool of “q” DRAM integrated circuits; wherein “p” and “q” comprise integer values.

Claim 9

Dependent Claim 95 words

The memory device as set forth in claim 6 , further comprising: a memory controller, coupled to at least one of the interface integrated circuit and the plurality of DRAM integrated circuits, for detecting occurrence of a pre-defined number of errors in working memory integrated circuits and for signaling to the interface integrated circuit to indicate the occurrence of the pre-defined number of errors; and wherein the interface integrated circuit is adapted to replace at least one DRAM integrated circuit of the working pool with at least one DRAM integrated circuit of the spare pool.

Claim 10

Dependent Claim 30 words

The memory device as set forth in claim 7 , wherein: the memory controller is further adapted to signal the occurrence of the pre-defined number of errors using in-band signaling.

Claim 11

Dependent Claim 31 words

The memory device as set forth in claim 7 , wherein: the memory controller is further adapted to signal the occurrence of the pre-defined number of errors using side band signaling.

Claim 12

Dependent Claim 115 words

A memory device for electrical connection to a memory bus, the memory device comprising: a plurality of dynamic random access memory (“DRAM”) integrated circuits, stacked in a vertical direction, each DRAM integrated circuit comprising a memory core of a plurality of cells and accessible at a first speed; and an interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed; wherein the plurality of DRAM integrated circuits comprise: a working pool of “p” DRAM integrated circuits; and a mirrored pool of “q” DRAM integrated circuits; wherein “p” and “q” comprise integer values.

Claim 13

Dependent Claim 115 words

A memory device for electrical connection to a memory bus, the memory device comprising: a plurality of dynamic random access memory (“DRAM”) integrated circuits, stacked in a vertical direction, each DRAM integrated circuit comprising a memory core of a plurality of cells and accessible at a first speed; and an interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed; wherein the plurality of DRAM integrated circuits comprise: a working pool of “p” DRAM integrated circuits; and a mirrored pool of “q” DRAM integrated circuits; wherein “p” and “q” comprise integer values.

Claim 14

Dependent Claim 95 words

The memory device as set forth in claim 10 , further comprising: a memory controller, coupled to at least one of the interface integrated circuit and the plurality of DRAM integrated circuits, for detecting occurrence of a pre-defined number of errors in working memory integrated circuits and for signaling to the interface integrated circuit to indicate the occurrence of the pre-defined number of errors; and wherein the interface integrated circuit is adapted to replace at least one DRAM integrated circuit of the working pool with at least one DRAM integrated circuit of the mirrored pool.

Claim 15

Dependent Claim 30 words

The memory device as set forth in claim 11 , wherein: the memory controller is further adapted to signal the occurrence of the pre-defined number of errors using in-band signaling.

Claim 16

Dependent Claim 31 words

The memory device as set forth in claim 11 , wherein: the memory controller is further adapted to signal the occurrence of the pre-defined number of errors using side band signaling.

Claim 17

Dependent Claim 14 words

The memory device as set forth in claim 10 , wherein: “p” equals “q”.

Claim 18

Dependent Claim 141 words

A memory device for electrical connection to a memory bus, the memory device comprising: a plurality of dynamic random access memory (“DRAM”) integrated circuits, stacked in a vertical direction, each DRAM integrated circuit comprising a memory core of a plurality of cells and accessible at a first speed; an interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed; and a memory scheme wherein the plurality of DRAM integrated circuits comprise; “p” DRAM integrated circuits used as a working memory device for storing data across the “p” DRAM integrated circuits; and at least one additional DRAM integrated circuit for storing additional information for the data stored in the “p” DRAM integrated circuits; wherein “p” comprises an integer value.

Claim 19

Dependent Claim 141 words

A memory device for electrical connection to a memory bus, the memory device comprising: a plurality of dynamic random access memory (“DRAM”) integrated circuits, stacked in a vertical direction, each DRAM integrated circuit comprising a memory core of a plurality of cells and accessible at a first speed; an interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed; and a memory scheme wherein the plurality of DRAM integrated circuits comprise; “p” DRAM integrated circuits used as a working memory device for storing data across the “p” DRAM integrated circuits; and at least one additional DRAM integrated circuit for storing additional information for the data stored in the “p” DRAM integrated circuits; wherein “p” comprises an integer value.

Claim 20

Dependent Claim 26 words

The memory device as set forth in claim 15 , wherein: the memory scheme comprises a RAID memory scheme; and the additional information comprises parity information.

Claim 21

Dependent Claim 17 words

The memory device as set forth in claim 15 , wherein: the additional information comprises prefetch information.

Claim 22

Dependent Claim 111 words

A memory device for electrical connection to a memory bus, the memory device comprising: a plurality of dynamic random access memory (“DRAM”) integrated circuits, stacked in a vertical direction, each DRAM integrated circuit comprising a memory core of a plurality of cells and accessible at a first speed; an interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed; and a socket, coupled to the stacked plurality of DRAM integrated circuits, for adding at least one additional DRAM integrated circuit to the stacked plurality of DRAM integrated circuits.

Claim 23

Dependent Claim 111 words

A memory device for electrical connection to a memory bus, the memory device comprising: a plurality of dynamic random access memory (“DRAM”) integrated circuits, stacked in a vertical direction, each DRAM integrated circuit comprising a memory core of a plurality of cells and accessible at a first speed; an interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed; and a socket, coupled to the stacked plurality of DRAM integrated circuits, for adding at least one additional DRAM integrated circuit to the stacked plurality of DRAM integrated circuits.

Claim 24

Dependent Claim 24 words

The memory device as set forth in claim 18 , wherein: the interface integrated circuit is stacked with the plurality of DRAM integrated circuits.

Claim 25

Dependent Claim 125 words

A memory device for electrical connection to a memory bus, the memory device comprising: a plurality of dynamic random access memory (“DRAM”) integrated circuits, stacked in a vertical direction, each DRAM integrated circuit comprising a memory core of a plurality of cells and accessible at a first speed; and an interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed; wherein the plurality of DRAM integrated circuits includes: at least one DRAM integrated circuit which was incorporated into the memory device at manufacturing time; and at least one DRAM integrated circuit which was incorporated into the memory device at a later time.

Claim 26

Dependent Claim 125 words

A memory device for electrical connection to a memory bus, the memory device comprising: a plurality of dynamic random access memory (“DRAM”) integrated circuits, stacked in a vertical direction, each DRAM integrated circuit comprising a memory core of a plurality of cells and accessible at a first speed; and an interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed; wherein the plurality of DRAM integrated circuits includes: at least one DRAM integrated circuit which was incorporated into the memory device at manufacturing time; and at least one DRAM integrated circuit which was incorporated into the memory device at a later time.

Claim 27

Dependent Claim 105 words

A memory device for electrical connection to a memory bus, the memory device comprising: a plurality of dynamic random access memory (“DRAM”) integrated circuits, stacked in a vertical direction, each DRAM integrated circuit comprising a memory core of a plurality of cells and accessible at a first speed; an interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed; a printed circuit board; and a socket for mounting the plurality of DRAM integrated circuits in a rank to the printed circuit board.

Claim 28

Dependent Claim 105 words

A memory device for electrical connection to a memory bus, the memory device comprising: a plurality of dynamic random access memory (“DRAM”) integrated circuits, stacked in a vertical direction, each DRAM integrated circuit comprising a memory core of a plurality of cells and accessible at a first speed; an interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed; a printed circuit board; and a socket for mounting the plurality of DRAM integrated circuits in a rank to the printed circuit board.

Claim 29

Dependent Claim 104 words

A memory device for use with a memory bus, the memory bus comprising: a plurality of dynamic random access memory (“DRAM”) integrated circuits, stacked in a vertical direction, each comprising a memory core of a plurality of cells accessible at low speed; and an interface integrated circuit for providing an interface, at a high speed relative to the low speed, between the DRAM integrated circuits and the memory bus; wherein the interface integrated circuit is adapted for providing a predetermined electrical load on the memory bus independent of a number of the DRAM integrated circuits to which the interface integrated circuit is electrically coupled.

Claim 30

Dependent Claim 104 words

Claim 31

Dependent Claim 107 words

A memory device for use with a memory bus, the memory bus comprising: means for stacking, in a vertical direction, a plurality of dynamic random access memory (“DRAM”) integrated circuits each comprising a memory core of a plurality of cells accessible at a first speed; and means for providing an interface between the DRAM integrated circuits and the memory bus at a speed greater than the first speed; wherein the means for providing the interface is adapted for providing a predetermined electrical load on the memory bus independent of a number of the DRAM integrated circuits to which the means for providing the interface is electrically coupled.

Claim 32

Dependent Claim 107 words

References Cited (Backward Citations)

US4646128A Cited

US4525921A Cited

US4841440A Cited

US4698748A Cited

US4780843A Cited

US4884237A Cited

US4710903A Cited

US4706166A Cited

US5083266A Cited

US4764846A Cited

US4982265A Cited

US4983533A Cited

US5104820A Cited

US6079025A Cited

US20040057317A1 Cited

US20020145900A1 Cited

US6862202B2 Cited

US5220672A Cited

US5388265A Cited

US5347428A Cited

US5843807A Cited

US5432729A Cited

US5581498A Cited

US5563086A Cited

US5702984A Cited

US5561622A Cited

US5502667A Cited

US5448511A Cited

USRE36839E Cited

US5943254A Cited

US5608262A Cited

US5901105A Cited

US5860106A Cited

US5752045A Cited

US5748914A Cited

US5590071A Cited

US5845108A Cited

US5884088A Cited

US5692202A Cited

US5680342A Cited

US6001671A Cited

US6070217A Cited

US5838165A Cited

US5926435A Cited

US5905688A Cited

US5973392A Cited

US6014339A Cited

US6338108B1 Cited

US6073223A Cited

US6088290A Cited

US6453400B1 Cited

US6075730A Cited

US5953215A Cited

US5835435A Cited

US5956233A Cited

US6298426B1 Cited

US6222739B1 Cited

US6970968B1 Cited

US6968419B1 Cited

US5963464A Cited

US6233192B1 Cited

US20030039158A1 Cited

US20010000822A1 Cited

US6338113B1 Cited

US6154370A Cited

US20020019961A1 Cited

US6353561B1 Cited

US6526471B1 Cited

US20020038405A1 Cited

US6587912B2 Cited

US6038673A Cited

US6442698B2 Cited

US20020124195A1 Cited

US6392304B1 Cited

US6594770B1 Cited

US20010021106A1 Cited

US6418034B1 Cited

US20020034068A1 Cited

US6657634B1 Cited

US6496440B2 Cited

US6327664B1 Cited

US6240048B1 Cited

US6252807B1 Cited

US7066741B2 Cited

US6878570B2 Cited

US6363031B2 Cited

US6166991A Cited

US6683372B1 Cited

US6772359B2 Cited

US6457095B1 Cited

US7045396B2 Cited

US20050210196A1 Cited

US20050044303A1 Cited

US20040186956A1 Cited

US20050193163A1 Cited

US20050166026A1 Cited

US20040256638A1 Cited

US20050156934A1 Cited

US20050207255A1 Cited

US20060067141A1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2011-05-27	2011-11-26	2012-05-27	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2015-05-27	2015-11-26	2016-05-27	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2019-05-27	2019-11-26	2020-05-27	$7700.00	Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag

Select Category

Notes (Optional)