Memory module system having multiple memory modules

Claim 2

A memory module system, comprising: a plurality of memory modules; a memory controller for selecting one of said memory modules; an external data bus provided commonly to said plurality of modules, said memory modules each including, a printed circuit board, a plurality of memory chips mounted on said printed circuit board, a plurality of internal data buses formed on said printed circuit board and corresponding to said plurality of memory chips, and each connected to a corresponding memory chip, and a plurality of first switching elements provided on said printed circuit board and corresponding to said plurality of internal data buses, and each connected between a corresponding internal data bus and said external data bus, said memory module system further comprising, a control circuit for turning on the plurality of first switching elements in a memory module selected by said memory controller, and turning off the plurality of first switching elements in the memory module other than the selected memory module wherein said control circuit includes a plurality of logic circuits corresponding to said plurality of memory modules, each for turning on the plurality of first switching elements in the corresponding memory module if said memory controller selects the corresponding memory module, and otherwise turning off the plurality of first switching elements, said memory controller applies a command signal representing a writing or reading mode to said plurality of logic circuits, said logic circuits each turning on the plurality of first switching elements in a corresponding memory module after a latency period since said command signal is received, and turning off said plurality of first switching elements after a burst length period since the turning on of said plurality of first switching elements.

Claim 3

The memory module system as recited in claim 1 , wherein each of said logic circuits is mounted on said printed circuit board in a corresponding memory module.

Claim 4

The memory module system as recited in claim 1 , wherein each of said logic circuits is built in at least one of a plurality of memory chips in a corresponding memory module.

Claim 5

A memory module system, comprising: a plurality of memory modules; a memory controller for selecting one of said memory modules; an external data bus provided commonly to said plurality of modules, said memory modules each including, a printed circuit board, a plurality of memory chips mounted on said printed circuit board, a plurality of internal data buses formed on said printed circuit board and corresponding to said plurality of memory chips, and each connected to a corresponding memory chip, and a plurality of first switching elements provided on said printed circuit board and corresponding to said plurality of internal data buses, and each connected between a corresponding internal data bus and said external data bus, said memory module system further comprising, a control circuit for turning on the plurality of first switching elements in a memory module selected by said memory controller, and turning off the plurality of first switching elements in the memory module other than the selected memory module, said control circuit includes a plurality of logic circuits corresponding to said plurality of memory modules, each built in at least one of a plurality of memory chips in a corresponding memory module, for turning on a plurality of first switching elements in corresponding memory module and otherwise turning off the plurality of first switching elements, wherein said memory controller applies a command signal representing a writing or reading mode to said plurality of logic circuits, said plurality of logic circuits each including, a write driver enable generation circuit for generating a write driver enable signal activated after a writing latency period since command signal representing the writing mode is received, and inactivated after a burst length period since the activation, an output enable generation circuit for generating an output enable signal activated after a column address strobe latency period since said command signal representing the reading mode is received, and inactivated after a burst length period since the activation, and an OR circuit receiving said write driver enable signal and said output enable signal, and each of the plurality of firs switching elements in each of said memory modules is a transistor having a gate to receive the output signal of the OR circuit in a corresponding logic circuit.

Claim 6

A memory module system, comprising: a plurality of memory modules; a memory controller for selecting one of said memory modules; an external data bus provided commonly to said plurality of modules, said memory modules each including, a printed circuit board, a plurality of memory chips mounted on said printed circuit board, a plurality of internal data buses formed on said printed circuit board and corresponding to said plurality of memory chips, and each connected to a corresponding memory chip, and a plurality of first switching elements provided on said printed circuit board and corresponding to said plurality of internal data buses, and each connected between a corresponding internal data bus and said external data bus, said memory module system further comprising, a control circuit for turning on the plurality of first switching elements in a memory module selected by said memory controller, and turning off the plurality of first switching elements in the memory module other than the selected memory module, said control circuit includes a plurality of logic circuits corresponding to said plurality of memory modules, each built in at least one of a plurality of memory chips in a corresponding memory module, for turning on a plurality of first switching elements in corresponding memory module and otherwise turning off the plurality of first switching elements, wherein said memory controller applies a command signal representing a writing or reading mode to said plurality of logic circuits, said plurality of logic circuits each including, a write driver enable generation circuit for generating a write driver enable signal activated after a writing latency period since command signal representing the writing mode is received, and inactivated after a burst length period since the activation, an output enable generation circuit for generating an output enable signal activated after a column address strobe latency period since said command signal representing the reading mode is received, and inactivated after a burst length period since the activation, and an OR circuit receiving said write driver enable signal and said output enable signal, and each of the plurality of firs switching elements in each of said memory modules is a transistor having a gate to receive the output signal of the OR circuit in a corresponding logic circuit.

Claim 7

A memory module system, comprising: a plurality of memory modules; a memory controller for selecting one of said memory modules; an external data bus provided commonly to said plurality of modules, said memory modules each including, a printed circuit board, a plurality of memory chips mounted on said printed circuit board, a plurality of internal data buses formed on said printed circuit board and corresponding to said plurality of memory chips, and each connected to a corresponding memory chip, and a plurality of first switching elements provided on said printed circuit board and corresponding to said plurality of internal data buses, and each connected between a corresponding internal data bus and said external data bus, said memory module system further comprising, a control circuit for turning on the plurality of first switching elements in a memory module selected by said memory controller, and turning off the plurality of first switching elements in the memory module other than the selected memory module, wherein said memory controller applies, to said control circuit, a command signal representing a writing or reading mode and a data transfer start signal representing the start of data transfer, said control circuit including, a plurality of first logic circuits corresponding to said plurality of memory modules, each built in at least one of the plurality of memory chips in a corresponding memory module, for generating a writing/reading end signal representing the end of writing/reading data to/from said plurality of memory chips in response to said command signal representing the writing or reading mode, and a plurality of second logic circuits corresponding to said plurality of memory modules and each mounted on the printed circuit board in a corresponding memory module for turning on a plurality of first switching elements in the corresponding memory module in response to said data transfer start signal, and turning off the plurality of first switching elements in response to said writing/reading end signal.

Claim 8

A memory module system, comprising: a plurality of memory modules; a memory controller for selecting one of said memory modules; an external data bus provided commonly to said plurality of modules, said memory modules each including, a printed circuit board, a plurality of memory chips mounted on said printed circuit board, a plurality of internal data buses formed on said printed circuit board and corresponding to said plurality of memory chips, and each connected to a corresponding memory chip, and a plurality of first switching elements provided on said printed circuit board and corresponding to said plurality of internal data buses, and each connected between a corresponding internal data bus and said external data bus, said memory module system further comprising, a control circuit for turning on the plurality of first switching elements in a memory module selected by said memory controller, and turning off the plurality of first switching elements in the memory module other than the selected memory module, wherein said memory controller applies, to said control circuit, a command signal representing a writing or reading mode and a data transfer start signal representing the start of data transfer, said control circuit including, a plurality of first logic circuits corresponding to said plurality of memory modules, each built in at least one of the plurality of memory chips in a corresponding memory module, for generating a writing/reading end signal representing the end of writing/reading data to/from said plurality of memory chips in response to said command signal representing the writing or reading mode, and a plurality of second logic circuits corresponding to said plurality of memory modules and each mounted on the printed circuit board in a corresponding memory module for turning on a plurality of first switching elements in the corresponding memory module in response to said data transfer start signal, and turning off the plurality of first switching elements in response to said writing/reading end signal.

Claim 9

The memory module system as recited in claim 5 , wherein said plurality of first logic circuits each include, a write driver enable generation circuit for generating a write driver enable signal activated after a writing latency period since said command signal representing the writing mode is received, and inactivated after a burst length period since the activation, an output enable signal generation circuit for generating an output enable signal activated after a column address strobe latency period since said command signal representing the read mode is received, and inactivated after a burst length period since the activation, an OR circuit receiving said write driver enable signal and said output enable signal, and an edge detection circuit for detecting an inactivation of an output signal from said OR circuit and generating a detection signal, each of said second logic circuits includes a flip-flop circuit set in response to said data transfer start signal and reset in response to said detection signal, each of the plurality of first switching elements in each of said memory modules includes a transistor having a gate to receive the output signal of a flip-flop circuit in a corresponding second logic circuit.

Claim 10

A memory module system, comprising: a plurality of memory modules; a memory controller for selecting one of said memory modules; an external data bus provided commonly to said plurality of modules, said memory modules each including, a printed circuit board, a plurality of memory chips mounted on said printed circuit board, a plurality of internal data buses formed on said printed circuit board and corresponding to said plurality of memory chips, and each connected to a corresponding memory chip, and a plurality of first switching elements provided on said printed circuit board and corresponding to said plurality of internal data buses, and each connected between a corresponding internal data bus and said external data bus, said memory module system further comprising, a control circuit for turning on the plurality of first switching elements in a memory module selected by said memory controller, and turning off the plurality of first switching elements in the memory module other than the selected memory module, further comprising an external data strobe bus provided commonly to said plurality of memory modules, said plurality of memory modules each including, an internal data strobe bus formed on said printed circuit board and provided commonly to said plurality of memory chips, and a second switching element provided on said printed circuit board and connected between said internal data strobe bus and said external data strobe bus, said control circuit turning on the second switching element in a memory module selected by said memory controller and turning off the second switching elements in the memory module other than the selected memory module.

Claim 11

A memory module system, comprising: a plurality of memory modules; a memory controller for selecting one of said memory modules; an external data bus provided commonly to said plurality of modules, said memory modules each including, a printed circuit board, a plurality of memory chips mounted on said printed circuit board, a plurality of internal data buses formed on said printed circuit board and corresponding to said plurality of memory chips, and each connected to a corresponding memory chip, and a plurality of first switching elements provided on said printed circuit board and corresponding to said plurality of internal data buses, and each connected between a corresponding internal data bus and said external data bus, said memory module system further comprising, a control circuit for turning on the plurality of first switching elements in a memory module selected by said memory controller, and turning off the plurality of first switching elements in the memory module other than the selected memory module, further comprising an external data strobe bus provided commonly to said plurality of memory modules, said plurality of memory modules each including, an internal data strobe bus formed on said printed circuit board and provided commonly to said plurality of memory chips, and a second switching element provided on said printed circuit board and connected between said internal data strobe bus and said external data strobe bus, said control circuit turning on the second switching element in a memory module selected by said memory controller and turning off the second switching elements in the memory module other than the selected memory module.

Claim 12

The memory module system as recited in claim 7 , wherein said plurality of memory modules each include a precharge circuit for precharging said internal data strobe bus to a ground potential or power supply potential when said second switching element is off.