US6327664B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Power management on a memory card having a signal processing element
Assignee: International Business Machines Corp
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Filing: 1999-04-30
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Granted: 2001-12-04
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Expires: 2019-04-30
Abstract
Abstract An improved memory module and its use in a computer system is provided. The module includes a DSP first and second individually addressable banks of memory chips. The first bank is configured to function principally under the control of the signal processing element and the second bank is configured to function principally under the control of a system memory controller, although all the portions of each of the memory banks is addressable by both the signal processing element and the system memory controller. Both banks of memory chips can be placed in at least one higher power state and at least one lower power state by either the system memory controller or the DSP. The activity of each bank is sensed while in the higher power state, and the condition of each of the banks is sensed with respect to any activity during operation of the memory bank at the higher power state. The power state of each bank can be changed by either the signal processing element or the system memory controller responsive to preselected conditions of each bank. Each memory bank is returned to a predetermined known condition when changing from a lower power state to a higher power state. This is especially important when the memory bank assigned to the system controller is placed in another state by the DSP.
Inventors
- 👤 Timothy J. Dell
- 👤 Bruce G. Hazelzet
- 👤 Mark W. Kellogg
- 👤 Christopher P. Miller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:30
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/325; G06F1/3275; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
240 words
A method of controlling the power utilized by a memory card in a computer system which includes a signal processing element on said card and at least one bank of memory chips, and wherein said at least one bank has at least a first portion thereof configured to principally function under the control of the signal processing element and a second portion configured to function principally under the control of a system memory controller in said computer system, and wherein each of said first and second portion of memory is addressable by both the signal processing element and said system memory controller, and wherein each portion of memory can be placed in at least a higher power state and a lower power state by either said system memory controller or said signal processing element, comprising the steps of; changing the power state of both said first portion of memory chips and said second portion of memory by either said signal processing element or said system controller responsive to preselected conditions of each portion, sensing the activity of each portion of memory chips before the power state is changed from said higher power state to said lower power state; sensing the condition of each of said portion of memory during any operation with respect to said memory bank; and always returning each memory portion to a predetermined known condition when changing from said lower power state to said higher power state.
Claim 2
Independent Claim
240 words
A method of controlling the power utilized by a memory card in a computer system which includes a signal processing element on said card and at least one bank of memory chips, and wherein said at least one bank has at least a first portion thereof configured to principally function under the control of the signal processing element and a second portion configured to function principally under the control of a system memory controller in said computer system, and wherein each of said first and second portion of memory is addressable by both the signal processing element and said system memory controller, and wherein each portion of memory can be placed in at least a higher power state and a lower power state by either said system memory controller or said signal processing element, comprising the steps of; changing the power state of both said first portion of memory chips and said second portion of memory by either said signal processing element or said system controller responsive to preselected conditions of each portion, sensing the activity of each portion of memory chips before the power state is changed from said higher power state to said lower power state; sensing the condition of each of said portion of memory during any operation with respect to said memory bank; and always returning each memory portion to a predetermined known condition when changing from said lower power state to said higher power state.
Claim 3
Dependent Claim
39 words
The invention as defined in claim 1 wherein there are at least first and second memory banks, and wherein said first memory bank constitutes said first portion of memory and said second memory bank constitutes said second memory portion.
Claim 4
Dependent Claim
46 words
The invention as defined in claim 2 wherein the second bank of memory chips is restored to the condition at the completion of the last access thereto by said system memory controller when said second bank of memory chips is accessed by the signal processing element.
Claim 5
Dependent Claim
29 words
The invention as defined in claim 2 wherein said first bank of memory chips is placed in a condition of inactive/standby before access thereto by said system memory controller.
Claim 6
Dependent Claim
27 words
The invention as defined in claim 1 wherein a wait signal is delivered to said system memory controller if the requested bank of memory chips is unavailable.
Claim 7
Dependent Claim
88 words
The invention as defined in claim 5 wherein said wait signal is generated if any of the following conditions exist: a) said second bank of memory chips is not in the condition of last access by the system memory controller; b) said first bank of memory chips is not in an inactive/standby condition; c) the system memory controller does not have physical access to either of said banks of memory; or d) either of the banks of memory chips do not have physical access to the system controller.
Claim 8
Dependent Claim
27 words
The invention as defined in claim 1 wherein an interrupt request signal is generated when the signal processor needs to be serviced by said system memory controller.
Claim 9
Dependent Claim
50 words
The invention as defined in claim 1 wherein there are at least three reduced power levels including a highest reduced power level which is a clock freeze mode, an intermediate reduced power level which is an inactive/standby mode, and a lowest reduced power level which is a self refresh mode.
Claim 10
Dependent Claim
263 words
In combination, a computer system including a system memory controller which generates clock enable signals, and a memory module, said module comprising a signal processing element, at least one bank of memory chips, wherein said at least one bank has at least a first portion thereof configured to principally function under the control of the signal processing element and a second portion configured to function principally under the control of a system memory controller in said computer system, each of said first and second portion of memory being addressable by both the signal processing element and said system memory controller, wherein each portion of memory can be placed in at least a higher power state and a lower power state by either said system memory controller or said signal processing element, logic circuitry to change the power state of both said first portion of memory chips and said second portion of memory by either said signal processing element or said system controller responsive to preselected conditions of each portion including circuitry to deliver clock enable signals selectively responsive directly to said system controller or responsive to the signal processing element, circuitry to sense the activity of each portion of memory chips before the power state is changed from said higher power state to said lower power state; circuitry to sense the condition of each of said portion of memory during any operation with respect to said memory bank; and circuitry to always return each memory portion to a predetermined known condition when changing from said lower power state to said higher power state.
Claim 11
Dependent Claim
263 words
In combination, a computer system including a system memory controller which generates clock enable signals, and a memory module, said module comprising a signal processing element, at least one bank of memory chips, wherein said at least one bank has at least a first portion thereof configured to principally function under the control of the signal processing element and a second portion configured to function principally under the control of a system memory controller in said computer system, each of said first and second portion of memory being addressable by both the signal processing element and said system memory controller, wherein each portion of memory can be placed in at least a higher power state and a lower power state by either said system memory controller or said signal processing element, logic circuitry to change the power state of both said first portion of memory chips and said second portion of memory by either said signal processing element or said system controller responsive to preselected conditions of each portion including circuitry to deliver clock enable signals selectively responsive directly to said system controller or responsive to the signal processing element, circuitry to sense the activity of each portion of memory chips before the power state is changed from said higher power state to said lower power state; circuitry to sense the condition of each of said portion of memory during any operation with respect to said memory bank; and circuitry to always return each memory portion to a predetermined known condition when changing from said lower power state to said higher power state.
Claim 12
Dependent Claim
39 words
The invention as defined in claim 9 wherein there are at least first and second memory banks, and wherein said first memory bank constitutes said first portion of memory and said second memory bank constitutes said second memory portion.
Claim 13
Dependent Claim
29 words
The invention as defined in claim 9 including logic circuitry to provide a wait signal to said system memory controller if the requested bank of memory chips is unavailable.
Claim 14
Dependent Claim
87 words
The invention as defined in claim 11 wherein said wait signal is generated if any of the following conditions exist: a) said second bank of memory chips is not in the condition of last access by the system memory controller; b) said first bank of memory chips is not in an inactive/standby condition; c) the system memory does not have physical access to either of said banks of memory; or d) either of the banks of memory chips do not have physical access to the system controller.
Claim 15
Dependent Claim
29 words
The invention as defined in claim 9 including logic circuitry to generate an interrupt request signal when the signal processor needs to be serviced by said system memory controller.
Claim 16
Dependent Claim
50 words
The invention as defined in claim 9 wherein there are at least three reduced power levels including a highest reduced power level which is a clock freeze mode, an intermediate reduced power level which is an inactive/standby mode, and a lowest reduced power level which is a self refresh mode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-12-03 | 2005-06-04 | 2005-12-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-12-03 | 2009-06-04 | 2009-12-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-12-03 | 2013-06-04 | 2013-12-04 | $7700.00 | Window Closed / Lapsed |