US5692202A — System, apparatus, and method for managing power …

Claim 1

Independent Claim 152 words

A computer system comprising: a bus; a processor having a bus controller coupled to said bus, said processor being configured to generate a signal indicating the beginning of a bus cycle; a bus activity monitor circuit coupled to said bus controller for generating a bus activity signal indicative of activity in said bus controller, said bus activity signal being asserted at least one clock cycle before said signal indicating the beginning of a bus cycle is asserted; a target controller, coupled to said bus controller, for controlling the exchange of information between said processor and a target circuit, said target controller having an input for receiving a control sequencing signal; and a power management circuit, for controlling a power consumption of said target controller, said power management circuit having an input, for receiving said bus activity signal and an output for generating, responsive to said bus activity signal, said control sequencing signal.

Claim 2

Dependent Claim 152 words

A computer system comprising: a bus; a processor having a bus controller coupled to said bus, said processor being configured to generate a signal indicating the beginning of a bus cycle; a bus activity monitor circuit coupled to said bus controller for generating a bus activity signal indicative of activity in said bus controller, said bus activity signal being asserted at least one clock cycle before said signal indicating the beginning of a bus cycle is asserted; a target controller, coupled to said bus controller, for controlling the exchange of information between said processor and a target circuit, said target controller having an input for receiving a control sequencing signal; and a power management circuit, for controlling a power consumption of said target controller, said power management circuit having an input, for receiving said bus activity signal and an output for generating, responsive to said bus activity signal, said control sequencing signal.

Claim 3

Dependent Claim 55 words

The computer system of claim 1 wherein said processor further includes a bus request queue for storing addresses, said bus request queue having a first gate for receiving a bus request (IBUSREQ) signal, said bus request queue having a second gate for generating a signal (BUSIDLE) indicative of an idle state of said bus controller.

Claim 4

Dependent Claim 38 words

The computer system of claim 2 wherein said bus activity monitor circuit has a first input, for receiving said IBUSREQ signal, a second input, for receiving said BUSIDLE signal, and an output for generating said bus activity signal.

Claim 5

Dependent Claim 37 words

The computer system of claim 1 wherein said power management circuit has a first input, for receiving said bus activity signal, a second input, for receiving a clock signal, and an output for generating said sequencing signal.

Claim 6

Dependent Claim 40 words

The computer system of claim 1 wherein said processor includes a resumption of activity circuit, said resumption of activity circuit generating said signal indicating the beginning of a bus cycle subsequent to a resumption of activity of said target controller.

Claim 7

Dependent Claim 25 words

The computer system of claim 5 wherein said resumption of activity circuit includes first flip-flop latch having an input for coupling to said IBUSREQ signal.

Claim 8

Dependent Claim 21 words

The computer system of claim 1 wherein said signal indicating the beginning of a bus cycle is an address valid signal.

Claim 9

Dependent Claim 36 words

The computer system of claim 3 wherein said bus activity monitor circuit includes an OR gate having a first input, for receiving said IBUSREQ signal a second input, for receiving said BUSIDLE signal, and an output.

Claim 10

Dependent Claim 50 words

The computer system of claim 6 further including a bus interface, said bus interface including a second flip-flop latch having an input for receiving said signal generated by said output of said bus activity monitor, said second flip flop latch further including an output for generating said bus activity signal.

Claim 11

Dependent Claim 42 words

The computer system of claim 1 wherein said power management circuit includes an AND gate having a first input, for receiving said bus activity signal, a second input, for receiving a clock signal, and an output for generating said control sequencing signal.

Claim 12

Dependent Claim 51 words

The computer system of claim 8 further including a second OR gate having a first input coupled to a DRAM refresh circuit, a second input coupled to said first bus queue, a third input coupled to said bus activity signal, and a fourth input coupled to a PCI clock control logic.

Claim 13

Dependent Claim 26 words

The computer system of claim 1 wherein said target controller is a dynamic random access memory (DRAM) controller and said target circuit is a DRAM memory.

Claim 14

Dependent Claim 25 words

The computer system of claim 11 wherein said target controller is a cache controller and said target circuit is a static random access memory (SRAM).

Claim 15

Dependent Claim 107 words

In a processor having a bus controller coupled to a bus, said bus being coupled to a target controller controlling the exchange of information between a target circuit and said bus, said processor including: a resumption of activity circuit that generates a signal indicating the beginning of a bus cycle, subsequent to a resumption of activity of said target controller; and a bus activity monitor circuit coupled to said bus controller for generating a bus activity signal indicative of activity in said bus controller, said bus activity signal being asserted at least one clock cycle before said signal indicating the beginning of a bus cycle is asserted.

Claim 16

Dependent Claim 107 words

In a processor having a bus controller coupled to a bus, said bus being coupled to a target controller controlling the exchange of information between a target circuit and said bus, said processor including: a resumption of activity circuit that generates a signal indicating the beginning of a bus cycle, subsequent to a resumption of activity of said target controller; and a bus activity monitor circuit coupled to said bus controller for generating a bus activity signal indicative of activity in said bus controller, said bus activity signal being asserted at least one clock cycle before said signal indicating the beginning of a bus cycle is asserted.

Claim 17

Dependent Claim 51 words

The processor of claim 14 further including a bus request queue for storing addresses, said bus request queue having a first gate for receiving a bus request (IBUSREQ) signal, said bus request queue having a second gate for generating a signal (BUSIDLE) indicative of an idle state of said bus controller.

Claim 18

Dependent Claim 37 words

The processor of claim 15 wherein said bus activity monitor circuit has a first input, for receiving said IBUSREQ signal, a second input, for receiving said BUSIDLE signal, and an output for generating said bus activity signal.

Claim 19

Independent Claim 81 words

A method for reducing power consumption of a circuit that is coupled to a processor via a bus, the method including the steps of: turning off power from the circuit if the processor is not using the bus; determining whether the processor indicates that it will use the bus; and if the processor indicates that it will use the bus, turning on power to the circuit at least one clock cycle before the processor indicates the beginning of a bus cycle.

Claim 20

Independent Claim 81 words

A method for reducing power consumption of a circuit that is coupled to a processor via a bus, the method including the steps of: turning off power from the circuit if the processor is not using the bus; determining whether the processor indicates that it will use the bus; and if the processor indicates that it will use the bus, turning on power to the circuit at least one clock cycle before the processor indicates the beginning of a bus cycle.

Claim 21

Dependent Claim 83 words

A computer system comprising: a bus; a target circuit coupled to the bus; a processor coupled to the bus, the processor including a resumption of activity control configured to generate a signal indicating beginning of a bus cycle, subsequent to turning on power to said target circuit; a circuit configured to generate a signal in response to which power is turned ON to the target circuit at least one clock cycle before the processor asserts the signal indicating beginning of the bus cycle.

Claim 22

Dependent Claim 83 words

A computer system comprising: a bus; a target circuit coupled to the bus; a processor coupled to the bus, the processor including a resumption of activity control configured to generate a signal indicating beginning of a bus cycle, subsequent to turning on power to said target circuit; a circuit configured to generate a signal in response to which power is turned ON to the target circuit at least one clock cycle before the processor asserts the signal indicating beginning of the bus cycle.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2000-11-24	2001-05-26	2001-11-25	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2004-11-24	2005-05-26	2005-11-25	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2008-11-24	2009-05-26	2009-11-25	$7700.00	Window Closed / Lapsed

System, apparatus, and method for managing power in a computer system

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