Power management system distinguishing between primary and secondary system activity

Claim 2

A power management unit for a computer system, wherein said computer system includes a processor rated for a maximum clock frequency, at least one peripheral device, and a clock generator for providing a CPU clock signal to said processor and a system clock signal to said peripheral device, wherein said power management unit comprises: a clock control unit configured to selectively vary the frequency of said CPU clock signal and said system clock signal; a system monitor configured to detect a primary activity of said computer system and a secondary activity of said computer system; and a power management state machine coupled to said clock control unit and to said system monitor, wherein said power management state machine includes a first state during which said clock control unit is invoked to drive said CPU clock signal at said maximum clock frequency, a second state during which said clock control unit is invoked to drive said CPU clock signal at a slower frequency, a third state during which said clock control unit is invoked to stop said CPU clock signal, and a transitory state during which said clock control unit is invoked to drive said CPU clock signal at said maximum clock frequency for a predetermined time, wherein said power management state machine reverts back to the previous state following said predetermined time, and wherein an occurrence of said primary activity causes said power management state machine to enter said first state, and wherein an occurrence of said secondary activity causes said power management state machine to enter said transitory state.

Claim 3

The power management unit as recited in claim 1 further comprising a time-out counter coupled to said system monitor and configured to determine whether, following a detection of a first primary activity by said system monitor, a subsequent primary activity has been detected by said system monitor within a first predetermined lapse of time.

Claim 4

The power management unit as recited in claim 2 wherein said power management state machine transitions from said first state to said second state if said subsequent primary activity does not occur within said first predetermined lapse of time.

Claim 5

The power management unit as recited in claim 2 wherein said power management state machine transitions from said second state to said third state if said subsequent primary activity does not occur within said first predetermined lapse of time.

Claim 6

The power management unit as recited in claim 2 wherein said power management state machine further includes a fourth state during which said clock control unit is invoked to stop said CPU clock signal and said system clock signal, and wherein said power management state machine transitions from said third state to said fourth state if said subsequent primary activity does not occur within said first predetermined lapse of time.

Claim 7

The power management unit as recited in claim 1 wherein said primary activity of said computer system includes a hard disk cycle.

Claim 8

The power management unit as recited in claim 1 wherein said primary activity of said computer system includes an activity of a floating-point coprocessor.

Claim 9

The power management unit as recited in claim 1 wherein said primary activity of said computer system includes a floppy disk cycle.

Claim 10

The power management unit as recited in claim 1 wherein said primary activity of said computer system includes a serial or parallel port cycle.

Claim 11

The power management unit as recited in claim 1 wherein said secondary activity of said computer system includes an occurrence of an interrupt.

Claim 12

The power management unit as recited in claim 1 wherein said secondary activity of said computer system includes an occurrence of a system management interrupt.

Claim 13

The power management unit as recited in claim 1 wherein said secondary activity of said computer system includes an occurrence of a timer tick interrupt.

Claim 14

The power management unit as recited in claim 1 wherein said power management state machine enters said transitory state if said secondary activity is detected while said power management state machine is in said second state, and wherein said power management state machine reverts back to said second state following said predetermined time.

Claim 15

The power management unit as recited in claim 1 wherein said power management unit enters said transitory state if said secondary activity is detected while said power management state machine is in said third state, and wherein said power management state machine reverts back to said third state following said predetermined time.

Claim 18

The method for managing power within a computer system as recited in claim 15 comprising the further step of stopping said system clock signal if said primary activity does not occur within a fourth predetermined time period following initiation of said step of stopping said CPU clock signal.

Claim 19

The method for managing power within a computer system as recited in claim 15 wherein said primary activity includes a hard disk cycle.

Claim 20

The method for managing power within a computer system as recited in claim 15 wherein said primary activity includes an activity of a floating-point coprocessor.

Claim 21

The method for managing power within a computer system as recited in claim 15 wherein said secondary activity includes an occurrence of an interrupt.

Claim 22

The method for managing power within a computer system as recited in claim 15 wherein said secondary activity includes an occurrence of a timer tick interrupt.

Claim 23

A power management unit for a computer system, wherein said computer system includes a processor rated for a maximum clock frequency, at least one peripheral device, and a clock generator for providing a CPU clock signal to said processor and a system clock signal to said peripheral device, wherein said power management unit comprises: a clock control unit configured to selectively vary the frequency of said CPU clock signal and said system clock signal; a system monitor configured to detect a primary activity of said computer system and a secondary activity of said computer system; and a power management state machine coupled to said clock control unit and to said system monitor, wherein said power management state machine includes a first state during which said clock control unit is invoked to drive said CPU clock signal at said maximum clock frequency, a second state during which said clock control unit is invoked to drive said CPU clock signal at a slower frequency, a third state during which said clock control unit is invoked to stop said CPU clock signal, and a transitory state during which said clock control unit is invoked to drive said CPU clock signal at said maximum clock frequency for a predetermined time; wherein an occurrence of said primary activity causes said power management state machine to enter said first state; and time-out counter circuitry coupled to said system monitor and to said power management state machine, wherein when said power management state machine is in said first state, said time-out counter circuitry is configured to determine whether a first subsequent primary activity, subsequent to said first primary activity, has been detected by said system monitor within a first predetermined lapse of time; wherein said power management state machine transitions from said first state to said second state if said first subsequent primary activity does not occur within said first predetermined lapse of time; wherein when said power management state machine is in said second state, said time-out counter circuitry is configured to determine whether a second subsequent primary activity, subsequent to said first subsequent primary activity, has been detected by said system monitor within a first predetermined lapse of time; wherein said power management state machine transitions from said second state to said third state if said first subsequent primary activity does not occur within said first predetermined lapse of time; wherein said power management state machine transitions from said second state to said transitory state if said secondary activity is detected while said power management state machine is in said second state, and wherein said power management state machine reverts back to said second state following said predetermined time; and wherein said power management state machine transitions from said third state to said transitory state if said secondary activity is detected while said power management state machine is in said third state, and wherein said power management state machine reverts back to said third state following said predetermined time.

Claim 24

A power management unit for a computer system, wherein said computer system includes a processor rated for a maximum clock frequency, at least one peripheral device, and a clock generator for providing a CPU clock signal to said processor and a system clock signal to said peripheral device, wherein said power management unit comprises: a clock control unit configured to selectively vary the frequency of said CPU clock signal and said system clock signal; a system monitor configured to detect a primary activity of said computer system and a secondary activity of said computer system; and a power management state machine coupled to said clock control unit and to said system monitor, wherein said power management state machine includes a first state during which said clock control unit is invoked to drive said CPU clock signal at said maximum clock frequency, a second state during which said clock control unit is invoked to drive said CPU clock signal at a slower frequency, a third state during which said clock control unit is invoked to stop said CPU clock signal, and a transitory state during which said clock control unit is invoked to drive said CPU clock signal at said maximum clock frequency for a predetermined time; wherein an occurrence of said primary activity causes said power management state machine to enter said first state; and time-out counter circuitry coupled to said system monitor and to said power management state machine, wherein when said power management state machine is in said first state, said time-out counter circuitry is configured to determine whether a first subsequent primary activity, subsequent to said first primary activity, has been detected by said system monitor within a first predetermined lapse of time; wherein said power management state machine transitions from said first state to said second state if said first subsequent primary activity does not occur within said first predetermined lapse of time; wherein when said power management state machine is in said second state, said time-out counter circuitry is configured to determine whether a second subsequent primary activity, subsequent to said first subsequent primary activity, has been detected by said system monitor within a first predetermined lapse of time; wherein said power management state machine transitions from said second state to said third state if said first subsequent primary activity does not occur within said first predetermined lapse of time; wherein said power management state machine transitions from said second state to said transitory state if said secondary activity is detected while said power management state machine is in said second state, and wherein said power management state machine reverts back to said second state following said predetermined time; and wherein said power management state machine transitions from said third state to said transitory state if said secondary activity is detected while said power management state machine is in said third state, and wherein said power management state machine reverts back to said third state following said predetermined time.