BIOS independent power management for portable computer

Claim 3

The method of claim 1 further comprising: said power control system deasserting said bus request signal to said complex for releasing control of said bus as master upon completion of said signal generation.

Claim 4

The method of claim 1 further comprising: monitoring said computer system for I/O activity when said at least one device is operating in said reduced power consumption state; said power control system issuing a bus request signal to said complex to gain control of said bus as master when said I/O activity is detected in response to said reduced power consumption state monitoring; and said power control system generating signals on said bus as master independent of said complex to said at least one device for removing said at least one device from said reduced power consumption state.

Claim 5

The method of claim 3 further comprising: said power control system deasserting said bus request signal to said complex for releasing control of said bus as master upon completion of said removal signal generation.

Claim 6

The method of claim 1 wherein said processor complex includes a central processing unit (CPU) and a CPU clock controller connected to said bus, the method further comprising said power control system generating signals on said system bus as master independent of said complex to said CPU clock controller for reducing the processing speed of said CPU.

Claim 7

The method of claim 5 wherein said CPU processing speed is reduced to 0 megahertz.

Claim 8

The method of claim 5 wherein said CPU processing speed is reduced to 3.125 megahertz.

Claim 9

The method of claim 1 wherein said predetermined interval is a default interval for each said at least one device.

Claim 10

The method of claim 1 wherein said predetermined interval is a user selected interval for each said at least one device.

Claim 11

The method of claim 1 wherein said at least one device comprises a display having a back light and a hard disk having a drive motor, the signal generating step further comprising: generating signals for turning off said display back light; and generating signals for turning off said drive motor.

Claim 14

A microcontroller connected to a system bus of a personal computer system, said microcontroller for managing power consumption of the system, the system including on said system bus a processor complex and input/output (I/O) devices each capable of operating in a reduced power consumption state, the microcontroller comprising: at least one signal line connected to at least one said device for receiving signals indicative of I/O activity of said at least one device; at least one control line connected to said complex for granting and relinquishing said microcontroller control of said system bus as master; logic for monitoring said at least one signal line for said signals indicative of said I/O activity; logic for setting a timer for a predetermined interval; logic for resetting said timer for said predetermined interval in the presence of said I/O activity responsive to said monitoring; logic for issuing a bus request signal on said at least one control line to said complex upon elapse of said interval to gain control of said bus as a master independent of said complex; logic for generating signals on said bus as master independent of said complex to said at least one device for placing said at least one device in said reduced power consumption state; and logic for deasserting said bus request signal on said at least one control line to said complex for releasing control of said bus as master upon completion of said signal generation.

Claim 15

A microcontroller connected to a system bus of a personal computer system, said microcontroller for managing power consumption of the system, the system including on said system bus a processor complex and input/output (I/O) devices each capable of operating in a reduced power consumption state, the microcontroller comprising: at least one signal line connected to at least one said device for receiving signals indicative of I/O activity of said at least one device; at least one control line connected to said complex for granting and relinquishing said microcontroller control of said system bus as master; logic for monitoring said at least one signal line for said signals indicative of said I/O activity; logic for setting a timer for a predetermined interval; logic for resetting said timer for said predetermined interval in the presence of said I/O activity responsive to said monitoring; logic for issuing a bus request signal on said at least one control line to said complex upon elapse of said interval to gain control of said bus as a master independent of said complex; logic for generating signals on said bus as master independent of said complex to said at least one device for placing said at least one device in said reduced power consumption state; and logic for deasserting said bus request signal on said at least one control line to said complex for releasing control of said bus as master upon completion of said signal generation.

Claim 16

The microcontroller of claim 12 wherein said processor complex includes a central processing unit (CPU), said microcontroller further comprising: a CPU clock controller connected to said system bus; logic for generating signals on said system bus as master independent of said complex to said CPU clock controller for reducing the processing speed of said CPU.

Claim 17

The microcontroller of claim 13 wherein said CPU processing speed is reduced to 0 megahertz.

Claim 18

The microcontroller of claim 13 wherein said CPU processing speed is reduced to 3.125 megahertz.

Claim 19

The microcontroller of claim 12 wherein said predetermined value is a default value.

Claim 20

The microcontroller of claim 12 wherein said predetermined interval is a user selected interval for each said at least one device.

Claim 21

The microcontroller of claim 12 further comprising: logic for monitoring said at least one signal line for said signals indicative of said I/O activity when said at least one device is in said reduced power consumption state; logic for issuing a bus request signal on said at least one control line to said complex to gain control of said bus as master when said I/O activity is detected in response to said reduced power consumption state monitoring; logic for generating signals on said bus as master independent of said complex to said at least one device for removing said at least one device from said reduced power consumption state; and logic for reasserting said bus request signal to said complex for releasing control of said bus as master upon completion of said removal signal generation.

Claim 22

A microcontroller connected to a system bus of a personal computer system, said microcontroller for managing power consumption of the system, the system including on said system bus a processor complex and input/output (I/O) devices each capable of operating in a reduced power consumption state, the microcontroller comprising: at least one signal line connected to at least one of said devices for receiving signals indicative of I/O activity of said at least one device; at least one control line connected to said complex for granting and relinquishing said microcontroller control of said system bus as master; logic for monitoring said at least one signal line for said signals indicative of said I/O activity; logic for setting a timer for a predetermined interval; logic for resetting said timer for said predetermined interval in the presence of said I/O activity responsive to said monitoring; logic for issuing a bus request signal on said at least one control line to said complex upon elapse of said interval to gain control of said bus as a master independent of said complex; logic for generating signals on said bus as master independent of said complex to said at least one device for placing said at least one device in said reduced power consumption state; logic for deasserting said bus request signal on said at least one control line to said complex for releasing control of said bus as master upon completion of said signal generation; logic for monitoring said at least one signal line for said signals indicative of said I/O activity when said at least one device is in said reduced power consumption state; logic for issuing a bus request signal on said at least one control line to said complex to gain control of said bus as master when said I/O activity is detected in response to said reduced power consumption state monitoring; logic for generating signals on said bus as master independent of said complex to said at least one device for removing said at least one device from said reduced power consumption state; and logic for deasserting said bus request signal to said complex for releasing control of said bus as master upon completion of said removal signal generation.

Claim 23

A microcontroller connected to a system bus of a personal computer system, said microcontroller for managing power consumption of the system, the system including on said system bus a processor complex and input/output (I/O) devices each capable of operating in a reduced power consumption state, the microcontroller comprising: at least one signal line connected to at least one of said devices for receiving signals indicative of I/O activity of said at least one device; at least one control line connected to said complex for granting and relinquishing said microcontroller control of said system bus as master; logic for monitoring said at least one signal line for said signals indicative of said I/O activity; logic for setting a timer for a predetermined interval; logic for resetting said timer for said predetermined interval in the presence of said I/O activity responsive to said monitoring; logic for issuing a bus request signal on said at least one control line to said complex upon elapse of said interval to gain control of said bus as a master independent of said complex; logic for generating signals on said bus as master independent of said complex to said at least one device for placing said at least one device in said reduced power consumption state; logic for deasserting said bus request signal on said at least one control line to said complex for releasing control of said bus as master upon completion of said signal generation; logic for monitoring said at least one signal line for said signals indicative of said I/O activity when said at least one device is in said reduced power consumption state; logic for issuing a bus request signal on said at least one control line to said complex to gain control of said bus as master when said I/O activity is detected in response to said reduced power consumption state monitoring; logic for generating signals on said bus as master independent of said complex to said at least one device for removing said at least one device from said reduced power consumption state; and logic for deasserting said bus request signal to said complex for releasing control of said bus as master upon completion of said removal signal generation.

Claim 24

The microcontroller of claim 19 wherein said processor complex includes a central processing unit (CPU), said microcontroller further comprising: a CPU clock controller connected to said system bus; logic for generating signals on said system bus as master independent of said complex to said CPU clock controller for reducing the processing speed of said CPU.

Claim 25

The microcontroller of claim 20 wherein said CPU processing speed is reduced to 0 megahertz.

Claim 26

The microcontroller of claim 20 wherein said CPU processing speed is reduced to 3.125 megahertz.

Claim 27

The microcontroller of claim 19 wherein said predetermined value is a default value.

Claim 28

The microcontroller of claim 19 wherein said predetermined interval is a user selected interval for each said at least one device.

Claim 31

The method of claim 25 wherein said at least one device comprises a display having a back light and a hard disk having a drive motor, the signal generating step further comprising: generating signals for turning off said display back light; and generating signals for turning off said drive motor.