Stanby mode controller utilizing microprocessor

Claim 1

A power conserving circuit for a two-way communications device having high and low power-level operating modes and having two operative states in the higher power mode, the device including a microprocessor, ROM memories, RAM memories and a battery, the circuit comprising in combination: delay means coupled to receiving and delaying a RAM enabling signal indicative of the operating mode of the device; first input means coupled to an output of the microprocessor for receiving a signal indicative of one of the two operative states of the device while operating in the high power mode; clock means for providing a low duty cycle signal; first logic means coupled to receive the output signals of the first input means, the clock means and the delay means for providing an operating level control signal for portions of the device; second input means coupled to an output of the microprocessor for providing memory select signals from the microprocessor; third input means coupled to the battery for providing a power input; fourth input means coupled to an output of the microprocessor for providing a first memory control signal; fifth input means coupled to an output of the microprocessor for providing a second memory control signal; second logic means coupled to receive the output signals of the first logic means and the second, third, and fourth input means for controlling power to ones of said ROM memories; third logic means coupled to receive the inverted output signals of the second input means and the output signals of the third, fourth and fifth input means and to the first logic means for providing an enabling signal to said RAM memories, the RAM enabling signal also being coupled to the delay means input to provide the mode indicative signal.