Abstract The disclosed system causes power to be removed from the memory for a chosen time duration after each time that the memory is used. The time duration can be chosen as desired and is specified by a ''''WAIT N'''' instruction. When this instruction appears, the power to the memory is removed therefrom and accesses to the memory are prevented. The time duration is entered into a register and the contents of this register are compared with the contents of a counter which has a clock pulse train applied thereto until equality is attained whereby an equality signal issues. The latter signal is applied to restore power to the memory and, with appropriate logic, permits accesses to the memory, read or write, for example. When the memory accessing is completed, the N units specified by the ''''WAIT N'''' instruction would be usable at the option of the program to control access to the memory and to remove power therefrom for the duration of N time units. A new ''''WAIT N'''' instruction can change the time duration.
A system for controlling the power consumption in a computer having a memory comprising: means for enabling said memory to be accessed for successively occurring (operations) only after respective predetermined time periods between said operations; means for provIding instructions in said computer which specify the durations of said periods; and means responsive to said instructions and to the initiation and completion of a memory access for respectively causing the supplying of electrical power to and the removing of electrical power from said memory.
Claim 2
Independent Claim
83 words
A system for controlling the power consumption in a computer having a memory comprising: means for enabling said memory to be accessed for successively occurring (operations) only after respective predetermined time periods between said operations; means for provIding instructions in said computer which specify the durations of said periods; and means responsive to said instructions and to the initiation and completion of a memory access for respectively causing the supplying of electrical power to and the removing of electrical power from said memory.
Claim 3
Dependent Claim
20 words
A system as defined in claim 1 wherein the durations of said time periods specified by said instructions are varied.
Claim 4
Dependent Claim
44 words
A system as defined in claim 2 wherein said memory access enabling means includes means for enabling a read access to said memory; means for enabling a write access to said memory, and means for enabling both read and write accesses to said memory.
Claim 5
Independent Claim
80 words
A system for controlling the power consumption in a computer having a memory comprising: means for providing instructions in said computer which specify a chosen time duration; first means responsive to said instructions for causing electrical power to be removed from said memory at the initiation of said duration and to be supplied to said memory at the termination of said duration; and second means responsive to said first means for preventing the accessing of said memory during said duration.
Claim 6
Independent Claim
80 words
A system for controlling the power consumption in a computer having a memory comprising: means for providing instructions in said computer which specify a chosen time duration; first means responsive to said instructions for causing electrical power to be removed from said memory at the initiation of said duration and to be supplied to said memory at the termination of said duration; and second means responsive to said first means for preventing the accessing of said memory during said duration.
Claim 7
Dependent Claim
69 words
A system as defined in claim 4 wherein said first means comprises: a register for receiving thereinto said time duration information from said instructions; a counter adapted to be cycled by pulses applied thereto; comparing means responsive to the contents of said register and said counter for providing an equality signal when said counter and register contents are equal, said equality signal occurring at the termination of said duration.
Claim 8
Dependent Claim
38 words
A system as defined in claim 5 wherein said second means comprises means responsive to said equality signal and accessing signals for said memory for enabling the accessing of said memory at the occurrence of said equality signal.