US5353420A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for decoding conditional jump instructions in a single clock in a computer processor
Assignee: Intel Corp
•
Filing: 1992-08-10
•
Granted: 1994-10-04
•
Expires: 2012-08-10
Abstract
Abstract In a pipelined microprocessor which includes a prefetch unit for obtaining a plurality of instructions to be processed; a decode unit having a prefix state machine for decoding prefixes and determining their lengths, a decode circuit for decoding instructions and generating microcode vectors to be executed, and apparatus for counting the length of an instruction; and a microcontroller for sequencing microcode vectors; the improvement including apparatus for detecting the appearance of a particular prefixed instruction, apparatus responsive to the detection of the particular prefixed instruction for disabling the prefix state machine, apparatus in the decode circuit for decoding the particular prefixed instruction and causing the decode circuit to generate microcode vectors for the instruction, and apparatus for generating a request to the microcontroller to handle microcode vectors generated.
Inventors
- 👤 Syed A. A. Zaidi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:44
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3818; G06F9/382; G06F9/30145; G06F9/30149; G06F9/3017; G06F9/30181; G06F9/30185; G06F9/3822
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
147 words
In a pipelined microprocessor which includes a prefetch unit for obtaining a plurality of instructions to be processed; a decode unit having a prefix state machine for decoding prefixes to instructions and determining their lengths, a decode circuit for decoding instructions and generating microcode vectors to be executed, the decode circuit being responsive to signals from the prefix state machine to vary the microcode vector generated, and means for counting the length of an instruction; and a microcontroller for sequencing microcode vectors; the improvement comprising: means for detecting the appearance of a particular prefixed instruction, means responsive to the detection of the particular prefixed instruction for disabling the prefix state machine, means in the decode circuit for decoding the particular prefixed instruction and causing the decode circuit to generate microcode vectors for the instruction, and means for generating a request to the microcontroller for microcode vectors generated.
Claim 2
Dependent Claim
147 words
In a pipelined microprocessor which includes a prefetch unit for obtaining a plurality of instructions to be processed; a decode unit having a prefix state machine for decoding prefixes to instructions and determining their lengths, a decode circuit for decoding instructions and generating microcode vectors to be executed, the decode circuit being responsive to signals from the prefix state machine to vary the microcode vector generated, and means for counting the length of an instruction; and a microcontroller for sequencing microcode vectors; the improvement comprising: means for detecting the appearance of a particular prefixed instruction, means responsive to the detection of the particular prefixed instruction for disabling the prefix state machine, means in the decode circuit for decoding the particular prefixed instruction and causing the decode circuit to generate microcode vectors for the instruction, and means for generating a request to the microcontroller for microcode vectors generated.
Claim 3
Dependent Claim
36 words
In a pipelined microprocessor as claimed in claim 1, the improvement further comprising means for causing the means for counting to include the length of a prefix in any length counted for the particular prefixed instruction.
Claim 4
Dependent Claim
54 words
In a pipelined microprocessor as claimed in claim 2, the means for causing the means for counting to include the length of a prefix in any length counted for the particular prefixed instruction comprising means for generating a signal in response to the detection of the particular prefixed instruction for increasing the length count.
Claim 5
Dependent Claim
51 words
In a pipelined microprocessor as claimed in claim 3, the improvement further comprising means for utilizing the signal generated in response to the detection of the particular prefixed instruction for increasing the length count to indicate that a byte of instruction exists in an unused field of an instruction being processed.
Claim 6
Dependent Claim
37 words
In a pipelined microprocessor as claimed in claim 3, the improvement further comprising means for utilizing a count of the length of an instruction to indicate the length of the instruction to remaining stages in the pipeline.
Claim 7
Dependent Claim
35 words
In a pipelined microprocessor as claimed in claim 3, the improvement further comprising means for utilizing a count of the length of an instruction to indicate the length of the instruction to a prefetch unit.
Claim 8
Dependent Claim
34 words
In a pipelined microprocessor as claimed in claim 3, the improvement further comprising means for increasing a count value for the opcode in order to provide correct extraction of another field of the instruction.
Claim 9
Independent Claim
126 words
The method of decoding a prefixed jump instruction in a single clock period in an Intel microprocessor having a state machine for detecting and decoding prefixes apart from the decoding of instructions of which they are a part in a decoder circuit, the decoder circuit normally generating a count of the bytes of the instruction not including any prefix bytes for generating a prefetch pointer, comprising the steps of detecting the presence of a prefixed jump instruction, disabling the state machine in response to the detection of the prefixed jump instruction, decoding the prefixed jump instruction in the decoder circuit, generating a microcode vector for the decoded prefixed jump instruction, and increasing the count of the number of bytes in the decoded instruction by one byte.
Claim 10
Independent Claim
126 words
The method of decoding a prefixed jump instruction in a single clock period in an Intel microprocessor having a state machine for detecting and decoding prefixes apart from the decoding of instructions of which they are a part in a decoder circuit, the decoder circuit normally generating a count of the bytes of the instruction not including any prefix bytes for generating a prefetch pointer, comprising the steps of detecting the presence of a prefixed jump instruction, disabling the state machine in response to the detection of the prefixed jump instruction, decoding the prefixed jump instruction in the decoder circuit, generating a microcode vector for the decoded prefixed jump instruction, and increasing the count of the number of bytes in the decoded instruction by one byte.
Claim 11
Dependent Claim
102 words
The method of decoding a prefixed jump instruction in a single clock period in an Intel microprocessor as claimed in claim 8 in which the step of increasing the count of the number of bytes in the decoded instruction by one byte comprises the step of providing a signal in response to the detection of the prefixed jump instruction to indiacate that a byte of instruction exists in an unused field of the decoded instruction, and counting the byte of instruction in the unused field of the decoded instruction in determining the count of the number of bytes in the decoded instruction.
Claim 12
Dependent Claim
35 words
The method of decoding a prefixed jump instruction in a single clock period in an Intel microprocessor as claimed in claim 8 in which the unused field of the decoded instruction is the immediate field.
References Cited (Backward Citations)
US4270167A
Cited
US4680698A
Cited
US4783734A
Cited
US4794526A
Cited
US5220669A
Cited
US5187791A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-03 | 1998-04-04 | 1998-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-03 | 2002-04-04 | 2002-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-03 | 2006-04-04 | 2006-10-04 | $7700.00 | Window Closed / Lapsed |