Computer system with variable length process to process communication

Claim 3

The method according to claim 1 wherein said concurrent processes are distributed in a computer system comprising a network of interconnected integrated circuit devices and said step of transmitting messages between concurrent processes further includes addressing communication channels of a first type to permit said data transfer to occur between processes on the same integrated circuit device and addressing channels of a second type to permit said data transfer to occur between two processes, one of which is on one integrated circuit device and the other of which is on a different integrated circuit device.

Claim 4

The method according to claim 1 further comprising establishing within said memory a respective workspace for each process, each workspace comprising a plurality of addressable memory locations, and recording in said locations of each workspace variables associated with the corresponding process, and wherein said identifying step in said scheduling step includes forming a linked list of said processes awaiting execution by providing in said workspace of each process on said linked list an indication of the first pointer for the respective next process scheduled for execution by the processor.

Claim 5

The method of operating concurrent processes according to claim 1 wherein the transfer of each message unit comprises transferring eight bits.

Claim 6

The method of operating concurrent processes according to claim 1 further including counting the number of message units transferred in a message and providing a signal when all message units in the message have been transferred.

Claim 7

A method according to claim 1 further including counting the number of message units transferred in a message and changing the indication of source address as the number of message units remaining to be transferred decreases.

Claim 8

The method according to claim 1 further comprising counting the number of message units transferred in a message and changing the indication of said destination address as the count of the number of message units remaining to be transferred decreases.

Claim 9

A microcomputer comprising memory and a processor coupled thereto and being operable to execute a plurality of concurrent processes in accordance with a plurality of program steps, said program steps comprising a plurality of instructions for sequential execution by the processor, each instruction including a set of function bits which designate a function to be executed by the processor wherein: (a) the microcomputer includes a scheduling means comprising (i) means for indicating the process which is being executed by the processor, said process being called the current process, (ii) means for identifying one or more processes which form a collection awaiting execution by the processor, and (iii) next process indicator means to indicate the next process in the collection to be executed by the processor, (b) said processor includes means responsive to a selected one of said instructions to stop execution of said current process by said processor and to respond to said next process indicator means to make the next process in the said collection the current process, whereby the processor is operated to share its processing time among said plurality of concurrent processes; and (c) said microcomputer includes message transmission means for effecting synchronized data transfer between two of said concurrent processes, said message transmission means comprising a plurality of communication channels, a status indicator to indicate the status of data communication through each channel and synchronizing means cooperating with said scheduling means to respond to said status indicator to interrupt a current process or add an interrupted process to said collection so that communication between two communicating processes is completed when the two processes are at corresponding program steps, said message transmission means further comprising (i) means for transferring from one addressable location to another a message unit of predetermined bit length, (ii) means responsive to execution of a message instruction to provide a count of the number of message units to be included in a message, (iii) source addressing means responsive to execution of a message instruction by an outputting process to indicate the address from which data is to be output and (iv) destination addressing means responsive to execution of a message instruction by an inputting process to indicate the address to which the data is to be input.

Claim 10

A microcomputer comprising memory and a processor coupled thereto and being operable to execute a plurality of concurrent processes in accordance with a plurality of program steps, said program steps comprising a plurality of instructions for sequential execution by the processor, each instruction including a set of function bits which designate a function to be executed by the processor wherein: (a) the microcomputer includes a scheduling means comprising (i) means for indicating the process which is being executed by the processor, said process being called the current process, (ii) means for identifying one or more processes which form a collection awaiting execution by the processor, and (iii) next process indicator means to indicate the next process in the collection to be executed by the processor, (b) said processor includes means responsive to a selected one of said instructions to stop execution of said current process by said processor and to respond to said next process indicator means to make the next process in the said collection the current process, whereby the processor is operated to share its processing time among said plurality of concurrent processes; and (c) said microcomputer includes message transmission means for effecting synchronized data transfer between two of said concurrent processes, said message transmission means comprising a plurality of communication channels, a status indicator to indicate the status of data communication through each channel and synchronizing means cooperating with said scheduling means to respond to said status indicator to interrupt a current process or add an interrupted process to said collection so that communication between two communicating processes is completed when the two processes are at corresponding program steps, said message transmission means further comprising (i) means for transferring from one addressable location to another a message unit of predetermined bit length, (ii) means responsive to execution of a message instruction to provide a count of the number of message units to be included in a message, (iii) source addressing means responsive to execution of a message instruction by an outputting process to indicate the address from which data is to be output and (iv) destination addressing means responsive to execution of a message instruction by an inputting process to indicate the address to which the data is to be input.

Claim 11

The microcomputer according to claim 8 wherein said means for identifying processes comprises a linked list indicating processes awaiting executing by said processor and means for indicating the last process on said linked list.

Claim 12

A microcomputer according to claim 9 wherein said memory provides for each process a respective workspace having a plurality of addressable locations, each of said workspaces including: (i) memory locations for recording variables associated with a corresponding process, (ii) a program stage indicator for the corresponding process and (iii) a portion of said linked list when the corresponding process itself is on said linked list, said linked list portion indicating the next process on said linked list.

Claim 13

The microcomputer of claim 8 wherein said message transmission means permits data transfer between processes executed on the same microcomputer, at least one of said communication channels comprising a memory location.

Claim 14

A microcomputer according to claim 11 in which the processor further includes means for copying directly a number of bytes of data indicated as a result of execution of a message instruction, directly from one byte address to another in the memory of the microcomputer.

Claim 15

A microcomputer according to claim 8, wherein the message transmission means is arranged to permit external data transmission between processes which are executed on different microcomputers and the or each channel comprises an external communication link.

Claim 16

A microcomputer according to claim 13, wherein each external communication link comprises store means for holding one byte of data.

Claim 17

A microcomputer according to claim 14, wherein each external communication link is arranged to transmit a succession of bytes without action by the processor.

Claim 18

A microcomputer according to claim 15, wherein each external communication link is arranged to deschedule a process which executes a message instruction using the address of that link and each link includes means for storing an indication of the number of bytes to be transmitted through the link together with a pointer to the source or destination address for the next byte of the message.

Claim 19

A microcomputer according to claim 16, in which each external communication link includes means for counting the number of bytes transmitted and providing an indication when all bytes have been transmitted.

Claim 20

A microcomputer according to claim 16, wherein each external communication link includes signal generating means to generate a request signal to the processor to reschedule the process involved in the message transmission when all bytes of the message have been transmitted.

Claim 21

A network of directly interconnected micro-computers each comprising a single integrated circuit microcomputer, each said microcomputer comprising memory and a processor coupled to said memory and being operable to execute a plurality of concurrent processes in accordance with a plurality of program steps, said program steps comprising a plurality of instructions for sequential execution by the processor, wherein: (a) each said microcomputer includes a scheduling means comprising (i) means for indicating the process which is being executed on said microcomputer, said process being called the current process, (ii) means for identifying one or more processes which form a collection awaiting execution by the processor, and (iii) next process indicator means to indicate the next process in the collection to be executed by the processor, (b) each said processor including means responsive to a selected one of said instructions to stop execution of said current process by said processor and to respond to said next process indicator means to make the next process in the said collection the current process whereby each processor is operated to share its processing time among said plurality of concurrent processes, and (c) each said microcomputer including message transmission means for effecting synchronized data transfer between two of said concurrent processes, said message transmission means comprising a plurality of communication channels, a status indicator to indicate the status of data communication through each channel and synchronizing means cooperating with said scheduling means to respond to said status indicator to interrupt a current process or add an interrupted process to said collection so that communication between two communicating processes is completed when the two processes are at corresponding program steps, said message transmission means further comprising (i) means for transferring from one addressable location to another a message unit of predetermined bit length, (ii) means responsive to execution of a message instruction to provide a count of the number of message units to be included in a message, (iii) source addressing means responsive to execution of a message instruction by an outputting process to indicate the address from which data is to be output and (iv) destination addressing means responsive to execution of a message instruction by an inputting process to indicate the address to which the data is to be input.

Claim 22

A network of directly interconnected micro-computers each comprising a single integrated circuit microcomputer, each said microcomputer comprising memory and a processor coupled to said memory and being operable to execute a plurality of concurrent processes in accordance with a plurality of program steps, said program steps comprising a plurality of instructions for sequential execution by the processor, wherein: (a) each said microcomputer includes a scheduling means comprising (i) means for indicating the process which is being executed on said microcomputer, said process being called the current process, (ii) means for identifying one or more processes which form a collection awaiting execution by the processor, and (iii) next process indicator means to indicate the next process in the collection to be executed by the processor, (b) each said processor including means responsive to a selected one of said instructions to stop execution of said current process by said processor and to respond to said next process indicator means to make the next process in the said collection the current process whereby each processor is operated to share its processing time among said plurality of concurrent processes, and (c) each said microcomputer including message transmission means for effecting synchronized data transfer between two of said concurrent processes, said message transmission means comprising a plurality of communication channels, a status indicator to indicate the status of data communication through each channel and synchronizing means cooperating with said scheduling means to respond to said status indicator to interrupt a current process or add an interrupted process to said collection so that communication between two communicating processes is completed when the two processes are at corresponding program steps, said message transmission means further comprising (i) means for transferring from one addressable location to another a message unit of predetermined bit length, (ii) means responsive to execution of a message instruction to provide a count of the number of message units to be included in a message, (iii) source addressing means responsive to execution of a message instruction by an outputting process to indicate the address from which data is to be output and (iv) destination addressing means responsive to execution of a message instruction by an inputting process to indicate the address to which the data is to be input.

Claim 23

A network according to claim 19 wherein each said means for identifying processes comprises a respective linked list indicating processes awaiting execution by said processor and means for indicating the last process on said linked list, and wherein said memory provides for each process on the microcomputer a respective workspace having a plurality of addressable locations, each of said workspaces including: (i) memory locations for recording variables associated with a corresponding process, (ii) a program stage indicator for the corresponding process and (iii) a portion of said linked list when the corresponding process is on said linked list, said linked list portion indicating the next process on said linked list.