Low power consumption type one-chip microcomputer having a plurality of peripheral circuits

Claim 2

A microcomputer comprising: a central processing unit; a plurality of peripheral circuits accessed by said central processing unit for a reading/writing of said peripheral circuits; selection means for generating a selection signal for each of said peripheral circuits, said selection signal being indicative of use or non-use of the corresponding peripheral circuit; and means for controlling, without using a program instruction of the microcomputer, permission and inhibition of application of a clock signal and a strobe signal to each of said peripheral circuits on the basis of said selection signal for said each of said peripheral circuits, wherein said selection means comprises at least one external terminal of the microcomputer.

Claim 3

A microcomputer according to claim 1, wherein said at least one external terminal is provided in a number corresponding to a number of said plurality of peripheral circuits.

Claim 4

A microcomputer according to claim 1, further comprising a voltage supply circuit and a ground, wherein bits of said selection information are provided by selectively connecting said at least one external terminal to one of said voltage supply circuit and said ground.

Claim 5

A microcomputer comprising: a central processing unit; a plurality of peripheral circuits accessed by said central processing unit for a reading/writing of said peripheral circuits; selection means for generating a selection signal for each of said peripheral circuits, said selection signal being indicative of use or non-use of the corresponding peripheral circuit; and means for controlling, without using a program instruction of the microcomputer, permission and inhibition of application of a clock signal and a strobe signal to each of said peripheral circuits on the basis of said selection signal for said each of said peripheral circuits, wherein said selection means includes memory means for holding selection information indicative of use or non-use of each of said peripheral circuits, said memory means supplying said selection signal to each of said peripheral circuits on the basis of the selection information held in said memory means, and at least one external terminal connected to said memory means for writing said selection information into said memory means only at a time of resetting the microcomputer.

Claim 6

A microcomputer comprising: a central processing unit; a plurality of peripheral circuits accessed by said central processing unit for a reading/writing of said peripheral circuits; selection means for generating a selection signal for each of said peripheral circuits, said selection signal being indicative of use or non-use of the corresponding peripheral circuit; and means for controlling, without using a program instruction of the microcomputer, permission and inhibition of application of a clock signal and a strobe signal to each of said peripheral circuits on the basis of said selection signal for said each of said peripheral circuits, wherein said selection means includes memory means for holding selection information indicative of use or non-use of each of said peripheral circuits, said memory means supplying said selection signal to each of said peripheral circuits on the basis of the selection information held in said memory means, and at least one external terminal connected to said memory means for writing said selection information into said memory means only at a time of resetting the microcomputer.

Claim 7

A microcomputer according to claim 4, wherein said memory means includes a plurality of bits, said plurality of bits being provided in a number corresponding to a number of said plurality of peripheral circuits.

Claim 8

A microcomputer according to claim 4, further comprising means for resetting said microcomputer, wherein said at least one external terminal reads said selection information indicative of the use or non-use of the respective peripheral circuit only at the time of resetting of said microcomputer.

Claim 9

A microcomputer according to claim 4, further comprising and address/data bus for coupling said at least one external terminal to each of said plurality of peripheral circuits and to said central processing unit, said microcomputer further comprising means for resetting said microcomputer coupled to said memory means, wherein said at least one external terminal reads said selection information indicative of the use or non-use of the respective peripheral circuit only at the time of resetting of said microcomputer.

Claim 10

A microcomputer comprising: a central processing unit; a plurality of peripheral circuits accessed by said central processing unit for a reading/writing of said peripheral circuits; selection means for generating a selection signal for each of said peripheral circuits, said selection signal being indicative of use or non-use of the corresponding peripheral circuit; and means for controlling, without using a program instruction of the microcomputer, permission and inhibition of application of a clock signal and a strobe signal to each of said peripheral circuits on the basis of said selection signal for said each of said peripheral circuits, wherein said selection means comprises at least one external terminal and wherein said controlling means comprises an AND gate for receiving a first input from said at least one external terminal and for receiving a second input from a clock generating circuit, and wherein said AND gate is selectively placed in one of an open condition and a closed condition based on said first and second inputs.

Claim 11

A microcomputer comprising: a central processing unit; a plurality of peripheral circuits accessed by said central processing unit for a reading/writing of said peripheral circuits; selection means for generating a selection signal for each of said peripheral circuits, said selection signal being indicative of use or non-use of the corresponding peripheral circuit; and means for controlling, without using a program instruction of the microcomputer, permission and inhibition of application of a clock signal and a strobe signal to each of said peripheral circuits on the basis of said selection signal for said each of said peripheral circuits, wherein said selection means comprises at least one external terminal and wherein said controlling means comprises an AND gate for receiving a first input from said at least one external terminal and for receiving a second input from a clock generating circuit, and wherein said AND gate is selectively placed in one of an open condition and a closed condition based on said first and second inputs.

Claim 12

A microcomputer according to claim 8, wherein said controlling means comprises a second AND gate for receiving a first input from said at least one external terminal and for receiving a second input from a strobe signal generating circuit, wherein said second AND gate is selectively placed in one of an open condition and a closed condition based on said first and second inputs respectively received from said at least one external terminal and said strobe signal generating circuit.