US4747041A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Automatic power control system which automatically activates and deactivates power to selected peripheral devices based upon system requirement
Assignee: Unisys Corp
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Filing: 1983-06-27
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Granted: 1988-05-24
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Expires: 2003-06-27
Abstract
Abstract A selective, non-manual power controller provides the selective, non-manual power control of various components of a data processing equipment from and reports the power status of such components to a central location. As opposed to pass power controllers which were limited to powering on or off all of the computer equipment controlled by a given controlling element, this invention provides a non-manual capability for remotely powering on or off any one or more components of a system or systems in a selective manner and providing the power status thereof. By being able to selectively activate or deactivate any or all of the components of a data processing system, the ability to conserve electrical energy is optimized. In many cases, a single component or a set of components are not used for extended periods of time, such as an entire production period or at least a large portion of a production period. For example, a peripheral subsystem or a particular peripheral device may be used solely for a certain type of job which is active for only a portion of a production period. Alternatively, a multiprocessor system may run as a unit processor system during evenings and weekends. The net result is a substantial saving in electrical energy that may be implemented from and reported to a central location.
Inventors
- 👤 Gary L. Engel
- 👤 Paul J. Georgeson
- 👤 Douglas R. Mueller
- 👤 John M. Quernemoen
- 👤 Bruce C. Todd
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:17
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3206; G06F1/3215; G06F1/3234; G06F1/325; Y; Y02; Y02D; Y02D30/00; Y02D30/50
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
298 words
A selective, automatic power control system for data processing equipment, said data processing equipment having a plurality of power controlling command sources connected to a plurality of controlled units via a plurality of interface connecting means, each of said interface connecting means comprising: selective automatic power control means connected to said plurality of power controlling command sources to automatically activate power to elected ones of said controlled units when such activation is required by any one of said plurality of power controlling command source means of said data processing equipment and to automatically deactivate power to said selected controlled units when their performance is no longer required by said data processing equipment, and including status indicating means to report back such activation/deactivation status of each of the plurality of controlled units to each of the plurality of command sources to thereby conserve the electricity previously required to constantly maintain power to controlled units during time periods when their operative performance is not required by said data processing equipment, said selective automatic power control means further comprising: (a) a common microcontroller bus; (b) a main microcontroller coupled thereto for control thereof; (c) an identical redundant microcontroller similarly coupled to said common microcontroller bus; (d) a memory means also coupled to said bus to provide storage; (e) a pair of parallel input/output means coupled to said bus to provide information to and from said bus; (f) a power control means coupled between said bus and a power source; (g) each of said parallel input/output means also having connected thereto a relay bus; (h) a plurality of relay cards connected to each of said relay buses; and (i) each of said relay cards having a plurality of power interfaces for individual connection to each of a plurality of peripheral control devices.
Claim 2
Dependent Claim
298 words
A selective, automatic power control system for data processing equipment, said data processing equipment having a plurality of power controlling command sources connected to a plurality of controlled units via a plurality of interface connecting means, each of said interface connecting means comprising: selective automatic power control means connected to said plurality of power controlling command sources to automatically activate power to elected ones of said controlled units when such activation is required by any one of said plurality of power controlling command source means of said data processing equipment and to automatically deactivate power to said selected controlled units when their performance is no longer required by said data processing equipment, and including status indicating means to report back such activation/deactivation status of each of the plurality of controlled units to each of the plurality of command sources to thereby conserve the electricity previously required to constantly maintain power to controlled units during time periods when their operative performance is not required by said data processing equipment, said selective automatic power control means further comprising: (a) a common microcontroller bus; (b) a main microcontroller coupled thereto for control thereof; (c) an identical redundant microcontroller similarly coupled to said common microcontroller bus; (d) a memory means also coupled to said bus to provide storage; (e) a pair of parallel input/output means coupled to said bus to provide information to and from said bus; (f) a power control means coupled between said bus and a power source; (g) each of said parallel input/output means also having connected thereto a relay bus; (h) a plurality of relay cards connected to each of said relay buses; and (i) each of said relay cards having a plurality of power interfaces for individual connection to each of a plurality of peripheral control devices.
Claim 3
Dependent Claim
276 words
A selective automatic power control system for a configuration of multiple data processing systems, each of which data processing systems includes a plurality of power controlling command sources and one or more input/output processors, each input/output processor coupled to all of said power controlling command sources within one of said data processing systems comprising: (a) a plurality of selective automatic control means, each coupled to all of said plurality of power controlling command sources of said multiple data processing systems; (b) a common peripheral control unit coupled to all of said plurality of selective automatic control means; (c) a plurality of peripheral devices; (d) each of said plurality of selective automatic control means further comprising: (1) a common microcontroller bus; (2) a main microcontroller coupled thereto for control thereof; (3) an identical redundant microcontroller similarly coupled to said common microcontroller bus; (4) a memory means also coupled to said bus to provide storage; (5) a pair of parallel input/output means coupled to said bus to provide information to and from said bus; (6) a power control means coupled between said bus and a power source; (7) each of said parallel input/output means also having connected thereto a relay bus; (8) a plurality of relay cards connected to each of said relay buses; and (9) each of said relay cards having a plurality of power interfaces for individual connection to each of a plurality of peripheral control devices wherein selected peripheral devices are automatically activated and/or deactivated by commands received via said plurality of power controlling command sources to thereby conserve the electricity previously used to maintain power to non-selected controlled peripheral devices during inactive time periods.
Claim 4
Dependent Claim
276 words
A selective automatic power control system for a configuration of multiple data processing systems, each of which data processing systems includes a plurality of power controlling command sources and one or more input/output processors, each input/output processor coupled to all of said power controlling command sources within one of said data processing systems comprising: (a) a plurality of selective automatic control means, each coupled to all of said plurality of power controlling command sources of said multiple data processing systems; (b) a common peripheral control unit coupled to all of said plurality of selective automatic control means; (c) a plurality of peripheral devices; (d) each of said plurality of selective automatic control means further comprising: (1) a common microcontroller bus; (2) a main microcontroller coupled thereto for control thereof; (3) an identical redundant microcontroller similarly coupled to said common microcontroller bus; (4) a memory means also coupled to said bus to provide storage; (5) a pair of parallel input/output means coupled to said bus to provide information to and from said bus; (6) a power control means coupled between said bus and a power source; (7) each of said parallel input/output means also having connected thereto a relay bus; (8) a plurality of relay cards connected to each of said relay buses; and (9) each of said relay cards having a plurality of power interfaces for individual connection to each of a plurality of peripheral control devices wherein selected peripheral devices are automatically activated and/or deactivated by commands received via said plurality of power controlling command sources to thereby conserve the electricity previously used to maintain power to non-selected controlled peripheral devices during inactive time periods.
Claim 5
Dependent Claim
263 words
A selective automatic power control system for controlling the operation of a plurality of peripheral devices of a data processing equipment comprising: (a) a master command source; (b) a system power controller connected thereto; (c) one or more command sources, all connected to said system power controller; (d) one or more subsystem power controllers each connected to each of said command sources; (e) said system power controller and each of said one or more subsystem power controllers all having a similar configuration, each comprising: (1) a common microcontroller bus; (2) a main microcontroller coupled thereto for control thereof; (3) an identical redundant microcontroller similarly coupled to said common microcontroller bus; (4) a memory means also coupled to said bus to provide storage; (5) a pair of parallel input/output means coupled to said bus to provide information to and from said bus; (6) a power control means coupled between said bus and a power source; (7) each of said parallel input/output means also having connected thereto a relay bus; (8) a plurality of relay cards connected to each of said delay buses; and (9) each of said relay cards having a plurality of power interfaces for individual connection to each of a plurality of peripheral control devices, wherein selected peripheral devices of the plurality of peripheral devices of said data processing equipment are automatically activated and/or deactivated by commands received from said system power controller and/or from one of said one or more subsystem power controllers to thereby conserve the electricity previously used to maintain power to non-selected peripheral devices during inactive time periods.
Claim 6
Dependent Claim
263 words
A selective automatic power control system for controlling the operation of a plurality of peripheral devices of a data processing equipment comprising: (a) a master command source; (b) a system power controller connected thereto; (c) one or more command sources, all connected to said system power controller; (d) one or more subsystem power controllers each connected to each of said command sources; (e) said system power controller and each of said one or more subsystem power controllers all having a similar configuration, each comprising: (1) a common microcontroller bus; (2) a main microcontroller coupled thereto for control thereof; (3) an identical redundant microcontroller similarly coupled to said common microcontroller bus; (4) a memory means also coupled to said bus to provide storage; (5) a pair of parallel input/output means coupled to said bus to provide information to and from said bus; (6) a power control means coupled between said bus and a power source; (7) each of said parallel input/output means also having connected thereto a relay bus; (8) a plurality of relay cards connected to each of said delay buses; and (9) each of said relay cards having a plurality of power interfaces for individual connection to each of a plurality of peripheral control devices, wherein selected peripheral devices of the plurality of peripheral devices of said data processing equipment are automatically activated and/or deactivated by commands received from said system power controller and/or from one of said one or more subsystem power controllers to thereby conserve the electricity previously used to maintain power to non-selected peripheral devices during inactive time periods.
Claim 7
Dependent Claim
214 words
A selective automatic power controller comprising: (a) a common microcontroller bus; (b) a main microcontroller coupled thereto for primary control thereof; (c) an identical redundant microcontroller also coupled to said common microcontroller bus, by an electrically isolated interconnection means, to simultaneously perform the same function as said main microcontroller; (d) clock logic means commonly coupled to said main and said redundant microcontrollers to concurrently provide clock signals thereto; (e) a comparison means connected between the main and redundant microcontrollers to provide an error generation signal to said clock logic means, which error generation signal causes the concurrently provided clock signals thereto to cease when inequality exists between said microcontrollers; (f) a memory means also coupled to said common microcontroller bus to provide storage; (g) a pair of parallel input/output means also coupled to said common microcontroller bus to provide information to and from said bus; (h) a power control means coupled between said common microcontroller bus and a power source; (i) each of said pair of parallel input/output means having respectively connected thereto a relay bus; (j) a plurality of relay cards connected to each of said relay busses; and (k) each of said relay cards having a plurality of power interfaces for individual connection to each of a plurality of peripheral control devices.
Claim 8
Dependent Claim
214 words
A selective automatic power controller comprising: (a) a common microcontroller bus; (b) a main microcontroller coupled thereto for primary control thereof; (c) an identical redundant microcontroller also coupled to said common microcontroller bus, by an electrically isolated interconnection means, to simultaneously perform the same function as said main microcontroller; (d) clock logic means commonly coupled to said main and said redundant microcontrollers to concurrently provide clock signals thereto; (e) a comparison means connected between the main and redundant microcontrollers to provide an error generation signal to said clock logic means, which error generation signal causes the concurrently provided clock signals thereto to cease when inequality exists between said microcontrollers; (f) a memory means also coupled to said common microcontroller bus to provide storage; (g) a pair of parallel input/output means also coupled to said common microcontroller bus to provide information to and from said bus; (h) a power control means coupled between said common microcontroller bus and a power source; (i) each of said pair of parallel input/output means having respectively connected thereto a relay bus; (j) a plurality of relay cards connected to each of said relay busses; and (k) each of said relay cards having a plurality of power interfaces for individual connection to each of a plurality of peripheral control devices.
References Cited (Backward Citations)
US3535560A
Cited
US4204249A
Cited
JPS5451745A
Cited
US4347575A
Cited
US4442492A
Cited
US4484258A
Cited
US4357665A
Cited
US4351023A
Cited
US4437154A
Cited
US4418333A
Cited
US4433249A
Cited
US4608661A
Cited
US4453208A
Cited
US4521871A
Cited
US4494207A
Cited
US4593349A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-24 | 1991-11-23 | 1992-05-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-24 | 1995-11-23 | 1996-05-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-24 | 1999-11-23 | 2000-05-24 | $7700.00 | Window Closed / Lapsed |