US4694393A
Expired / Lapsed
US
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Peripheral unit for a microprocessor system
Assignee: Sharp Corp
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Filing: 1984-06-11
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Granted: 1987-09-15
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Expires: 2004-06-11
Abstract
Abstract A peripheral unit for a microprocessor system connected to a microprocessor comprises means for selecting whether an operation of the peripheral unit is to be halted in response to an inputted signal, and means for prohibiting the supply of a signal for activating the peripheral unit in response to the output of the selecting means. The peripheral unit, further, comprises means for canceling the operation of the prohibiting means to supply the signal for activating the peripheral unit in response to a second inputted signal. The peripheral unit and the microprocessor are constructed of CMOS transistors.
Inventors
- 👤 Takaaki Hirano
- 👤 Setsufumi Kamuro
- 👤 Akira Yamaguchi
- 👤 Junichi Tanimoto
- 👤 Mikiro Okada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:58
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3206; G06F1/3215; G06F1/3234; G06F1/325
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
61 words
A peripheral unit for a microprocessor system including a microprocessor, comprising: means, responsive to a halt-operation instruction from the microprocessor, for outputting a halt-operation signal; means, responsive to an activation signal from the microprocessor, for producing an internal clock signal for activating said peripheral unit; and means, responsive to said halt-operation signal, for inhibiting the production of said internal clock signal.
Claim 2
Dependent Claim
61 words
A peripheral unit for a microprocessor system including a microprocessor, comprising: means, responsive to a halt-operation instruction from the microprocessor, for outputting a halt-operation signal; means, responsive to an activation signal from the microprocessor, for producing an internal clock signal for activating said peripheral unit; and means, responsive to said halt-operation signal, for inhibiting the production of said internal clock signal.
Claim 3
Dependent Claim
34 words
The peripheral unit of claim 1, wherein said means responsive to said halt-operation signal further comprises means, responsive to a read-out signal from the microprocessor, for reenabling the production of said internal clock signal.
Claim 4
Dependent Claim
18 words
The peripheral unit of claim 1, wherein the peripheral unit and the microprocessor are constructed of CMOS transistors.
Claim 5
Dependent Claim
22 words
The peripheral unit of claim 1, wherein the activation signal from the microprocessor for activating the peripheral unit is a clock signal.
Claim 6
Dependent Claim
20 words
The peripheral unit of claim 1, wherein said means responsive to said halt-operation signal is a register or a flip-flop.
Claim 7
Dependent Claim
19 words
The peripheral unit of claim 1, wherein said means for producing an internal clock signal is a gate circuit.
Claim 8
Dependent Claim
19 words
The peripheral unit of claim 1, wherein said means for producing an internal clock signal is an AND gate.
References Cited (Backward Citations)
US4041471A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-09-14 | 1991-03-16 | 1991-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-09-14 | 1995-03-16 | 1995-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-09-14 | 1999-03-16 | 1999-09-15 | $7700.00 | Window Closed / Lapsed |