US6038673A
Expired / Lapsed
US
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Computer system with power management scheme for DRAM devices
Assignee: Intel Corp
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Filing: 1998-11-03
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Granted: 2000-03-14
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Expires: 2018-11-03
Abstract
Abstract A computer system employs DRAM devices in a memory sub-system, which devices are assigned into particular pools corresponding to different power consumption states with a most-recently-accessed (MRA) device being assigned to an active pool and placed at the top of a stack structure. A LRA device in the active pool is evicted from the active pool and placed in a standby pool when the active pool is full and the processor accesses another device, which is not currently assigned to the active pool. A LRA device of the standby pool gets evicted into a nap pool upon one of two conditions: either a timeout occurs, or the standby and active pools are full and the processor accesses another device, which is not currently assigned to either the active or standby pools.
Inventors
- 👤 Samuel D. Benn
- 👤 Michael W. Williams
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:24
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3206; G06F1/3215; G06F1/3225; G06F1/3234; G06F1/325; G06F1/3275; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
174 words
A computer system comprising: a central processing unit (CPU); a memory sub-system that includes DRAM devices coupled to the CPU, the CPU selectively accessing information stored in the DRAM devices; logic circuitry that assigns the DRAM devices to active, standby, or nap pools based on temporal access of each device by the CPU, the active, standby, and nap pools corresponding to power consumption states of the DRAM devices; and means for storing an active pool size to define a maximum number of devices of the active pool, and a standby pool size to define a maximum number of devices of the standby pool; wherein the logic circuitry includes a stack structure associated with the active and standby pools in which a most recently accessed (MRA) device is placed in the active pool at a top-of-stack (TOS) position, a least-recently accessed (LRA) device in the active pool being evicted to the standby pool when the active pool is full and the CPU accesses another device, which is neither assigned to the standby nor nap pools.
Claim 2
Dependent Claim
174 words
A computer system comprising: a central processing unit (CPU); a memory sub-system that includes DRAM devices coupled to the CPU, the CPU selectively accessing information stored in the DRAM devices; logic circuitry that assigns the DRAM devices to active, standby, or nap pools based on temporal access of each device by the CPU, the active, standby, and nap pools corresponding to power consumption states of the DRAM devices; and means for storing an active pool size to define a maximum number of devices of the active pool, and a standby pool size to define a maximum number of devices of the standby pool; wherein the logic circuitry includes a stack structure associated with the active and standby pools in which a most recently accessed (MRA) device is placed in the active pool at a top-of-stack (TOS) position, a least-recently accessed (LRA) device in the active pool being evicted to the standby pool when the active pool is full and the CPU accesses another device, which is neither assigned to the standby nor nap pools.
Claim 3
Dependent Claim
52 words
The computer system of claim 1 further comprising: means for pointing to a LRA device in the standby pool, the LRA device in the standby pool being evicted to the nap pool when the active and standby pools are full and the CPU accesses another device that is in the nap pool.
Claim 4
Dependent Claim
33 words
The computer system of claim 1 wherein the logic circuitry further includes: timer means for evicting the LRA device in the standby pool to the nap pool after a selected duration of inactivity.
Claim 5
Dependent Claim
37 words
The computer system of claim 3 wherein the timer means evicts the LRA of the active pool into either the standby or nap pools when the standby pool is empty and the selected duration of inactivity elapses.
Claim 6
Dependent Claim
27 words
The computer system of claim 1 wherein an access by the CPU to a device in the active pool does not affect the standby or nap pools.
Claim 7
Dependent Claim
21 words
The computer system of claim 1 wherein the selected duration of inactivity comprises a number of clock cycles of the CPU.
Claim 8
Dependent Claim
18 words
The computer system of claim 1 wherein the storage means comprises one or more registers of the CPU.
Claim 9
Dependent Claim
25 words
The computer system of claim 1 wherein the storage means comprises a memory location associated with a basic input/output system (BIOS) or the computer system.
Claim 10
Dependent Claim
12 words
The computer system of claim 1 wherein the storage means is programmable.
Claim 11
Dependent Claim
114 words
A computer system comprising: a bus; a processor coupled to the bus; a plurality of DRAM devices coupled to the bus, the processor accessing the DRAM devices via the bus; a controller that assigns each DRAM device to one of a plurality of pools according to a power consumption state of the DRAM device, the plurality of pools including an active pool that contains devices in a high power consumption state and a nap pool that contains devices in a low power consumption state, the controller having a stack, with a most-recently accessed (MRA) device being assigned to a top-of-stack (TOS) position in the active pool, unaccessed devices being assigned to the nap pool.
Claim 12
Dependent Claim
114 words
A computer system comprising: a bus; a processor coupled to the bus; a plurality of DRAM devices coupled to the bus, the processor accessing the DRAM devices via the bus; a controller that assigns each DRAM device to one of a plurality of pools according to a power consumption state of the DRAM device, the plurality of pools including an active pool that contains devices in a high power consumption state and a nap pool that contains devices in a low power consumption state, the controller having a stack, with a most-recently accessed (MRA) device being assigned to a top-of-stack (TOS) position in the active pool, unaccessed devices being assigned to the nap pool.
Claim 13
Dependent Claim
62 words
The computer system of claim 10 wherein the plurality of pools further includes a standby pool that contains devices in an intermediate power consumption state, a least-recently accessed (LRA) device of the active pool being evicted to the standby pool when the active pool is full and the processor accesses another device, which is neither assigned to the standby nor nap pool.
Claim 14
Dependent Claim
29 words
The computer system of claim 11 further comprising: a first storage location to store an active pool size that defines a maximum number of devices for the active pool.
Claim 15
Dependent Claim
29 words
The computer system of claim 12 further comprising: a second storage location to store a standby pool size that defines a maximum number of devices for the standby pool.
Claim 16
Dependent Claim
20 words
The computer system of claim 13 further comprising: a pointer that points to a LRA device of the standby pool.
Claim 17
Dependent Claim
29 words
The computer system of claim 14 further comprising: a timer that evicts the LRA device of the standby pool to the nap pool after a selected duration of inactivity.
Claim 18
Dependent Claim
37 words
The computer system of claim 15 wherein the timer means evicts the LRA of the active pool into either the standby or nap pools when the standby pool is empty and the selected duration of inactivity elapses.
Claim 19
Dependent Claim
40 words
The computer system of claim 14 wherein the LRA device in the standby pool is evicted to the nap pool when the active and standby pools are full and the processor accesses another device that is in the nap pool.
Claim 20
Dependent Claim
27 words
The computer system of claim 11 wherein an access by the processor to a device in the active pool does not affect the standby or nap pools.
Claim 21
Dependent Claim
26 words
The computer system of claim 10 wherein upon a reset condition of the computer system, all of the DRAM devices are assigned to the nap pool.
Claim 22
Independent Claim
166 words
A method of power management for a computer system including a processor that accesses information stored in DRAM devices, the method comprising the steps of: (a) assigning a most-recently accessed (MRA) device to an active pool associated with a stack, the MRA device being at a top-of-stack (TOS) position, the active pool having a predetermined size with a certain stack position representing a least-recently accessed (LRA) device in the active pool; (b) evicting the LRA device from the active pool into a standby pool when the active pool is full and the processor accesses another device, which is not currently assigned to the active pool; (c) identifying a LRA device in the standby pool; and (d) evicting the LRA device from the standby pool into a nap pool upon a timeout condition; wherein the active, standby and nap pools corresponding to power consumption states with the active pool corresponding to a high power consumption state and the nap pool corresponding to a low power consumption state.
Claim 23
Independent Claim
166 words
A method of power management for a computer system including a processor that accesses information stored in DRAM devices, the method comprising the steps of: (a) assigning a most-recently accessed (MRA) device to an active pool associated with a stack, the MRA device being at a top-of-stack (TOS) position, the active pool having a predetermined size with a certain stack position representing a least-recently accessed (LRA) device in the active pool; (b) evicting the LRA device from the active pool into a standby pool when the active pool is full and the processor accesses another device, which is not currently assigned to the active pool; (c) identifying a LRA device in the standby pool; and (d) evicting the LRA device from the standby pool into a nap pool upon a timeout condition; wherein the active, standby and nap pools corresponding to power consumption states with the active pool corresponding to a high power consumption state and the nap pool corresponding to a low power consumption state.
Claim 24
Dependent Claim
16 words
The method according to claim 20 wherein the standby pool is also associated with the stack.
Claim 25
Dependent Claim
19 words
The method according to claim 20 wherein the timeout condition comprises a number of clock cycles of the processor.
Claim 26
Dependent Claim
19 words
The method according to claim 20 further comprising the initial step of: programming the predetermined size into a register.
Claim 27
Dependent Claim
59 words
The method according to claim 20 wherein the standby pool also has a predetermined size, and further comprising the step of: evicting the LRA device from the standby pool to the nap pool when the standby and active pools are full and the processor accesses another device, which is not currently assigned to either the active or standby pools.
References Cited (Backward Citations)
US4616346A
Cited
US5396635A
Cited
US5473767A
Cited
US5687123A
Cited
US5754436A
Cited
US5953246A
Cited
US5822597A
Cited
US5860106A
Cited
US5826092A
Cited
US5740118A
Cited
US5721935A
Cited
US5796992A
Cited
US5740454A
Cited
US5884088A
Cited
US5784628A
Cited
US5822600A
Cited
US5913067A
Cited
US5845140A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-03-14 | 2003-09-13 | 2004-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-03-14 | 2007-09-13 | 2008-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-03-14 | 2011-09-13 | 2012-03-14 | $7700.00 | Window Closed / Lapsed |