US5860106A
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US
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Method and apparatus for dynamically adjusting power/performance characteristics of a memory subsystem
Assignee: Intel Corp
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Filing: 1995-07-13
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Granted: 1999-01-12
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Expires: 2015-07-13
Abstract
Abstract An apparatus and method for dynamically adjusting the power/performance characteristics of a memory subsystem. Since the memory subsystem access requirements are heavily dependent on the application being executed, static methods of enabling or disabling the individual memory system components (as are used in prior art) are less than optimal from a power consumption perspective. By dynamically tracking the behavior of the memory subsystem, the invention predicts the probability that the next event will have certain characteristics, such as whether it will result in a memory cycle that requires the attention of a cache memory, whether that memory cycle will result in a cache memory hit, and whether a DRAM page hit in main memory will occur if the requested data is not in one of the levels of cache memory. Based on these probabilities, the invention dynamically enables or disables components of the subsystem. By intelligently adjusting the state of these components, significant power savings are achieved without degradation in performance.
Inventors
- 👤 Stanley J. Domen
- 👤 Dileep R. Idate
- 👤 Stephen H. Gunther
- 👤 George Thangadurai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 04:54
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G06; G06F; G06F12/00; G06F12/02; G06F12/0215; G06F12/08; G06F12/0802; G06F2212/00; G06F2212/10; G06F2212/1028; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
98 words
A computer system comprising: a processor; a memory system including a cache; at least one bus coupled to the memory system and to the processor; and an optimization logic that predicts a probability of an event in a memory subsystem wherein the optimization logic enables a tag array if the probability of the event reaches a first predetermined level, enables a data cache if the probability of the event reaches a second predetermined level and only enables the data cache if the event actually occurs if the probability of the event has not reached the second predetermined level.
Claim 2
Dependent Claim
98 words
A computer system comprising: a processor; a memory system including a cache; at least one bus coupled to the memory system and to the processor; and an optimization logic that predicts a probability of an event in a memory subsystem wherein the optimization logic enables a tag array if the probability of the event reaches a first predetermined level, enables a data cache if the probability of the event reaches a second predetermined level and only enables the data cache if the event actually occurs if the probability of the event has not reached the second predetermined level.
Claim 3
Dependent Claim
58 words
The computer system of claim 1 wherein the optimization logic comprises: a plurality of comparators; and a plurality of counters for tracking parameters coupled to the plurality of comparators which together predict the probability of an event in the memory subsystem wherein the parameters tracked include bus utilization and hit/miss occurrences for a portion of the memory subsystem.
Claim 4
Dependent Claim
43 words
The computer system of claim 1 wherein the memory subsystem comprises a main memory and the optimization logic dynamically enables a memory access mode to be one of page mode and single access mode base on a predicted probability of a second event.
Claim 5
Dependent Claim
116 words
A computer system comprising: a processor; a memory system; at least one bus; means for tracking behavior of a memory subsystem; means for predicting the occurrence of an event in the memory subsystem based on the tracked behavior; and means for dynamically adjusting a mode of operation of the memory subsystem responsive to the predicting means wherein the means for dynamically adjusting enables a tag array if the probability of the event reaches a first predetermined level, enables a data cache if the probability of the event reaches a second predetermined level, and only enables the data cache if the event actually occurs if the probability of the event has not reached the second predetermined level.
Claim 6
Dependent Claim
116 words
A computer system comprising: a processor; a memory system; at least one bus; means for tracking behavior of a memory subsystem; means for predicting the occurrence of an event in the memory subsystem based on the tracked behavior; and means for dynamically adjusting a mode of operation of the memory subsystem responsive to the predicting means wherein the means for dynamically adjusting enables a tag array if the probability of the event reaches a first predetermined level, enables a data cache if the probability of the event reaches a second predetermined level, and only enables the data cache if the event actually occurs if the probability of the event has not reached the second predetermined level.
Claim 7
Independent Claim
98 words
A method of dynamically adjusting characteristics of a computer system having a processor coupled to a memory subsystem including a cache, comprising the steps of: recording information of prior activity of the memory subsystem; predicting a probability of a cache hit on a next transaction with the cache; enabling a tag array if the probability of a cache hit reaches a predetermined level; enabling a data cache if the hit probability reaches a second predetermined level; and enabling the data cache only if a hit actually occurs if the hit probability has not reached the second predetermined level.
Claim 8
Independent Claim
98 words
A method of dynamically adjusting characteristics of a computer system having a processor coupled to a memory subsystem including a cache, comprising the steps of: recording information of prior activity of the memory subsystem; predicting a probability of a cache hit on a next transaction with the cache; enabling a tag array if the probability of a cache hit reaches a predetermined level; enabling a data cache if the hit probability reaches a second predetermined level; and enabling the data cache only if a hit actually occurs if the hit probability has not reached the second predetermined level.
Claim 9
Dependent Claim
52 words
The method of claim 5 wherein the memory subsystem comprises a memory organized in pages and wherein the method further comprises the steps of: predicting a probability of a memory page hit on a next transaction; and enabling RAS active mode if the probability of a page hit exceeds a predetermined level.
Claim 10
Dependent Claim
30 words
The method of claim 6 wherein the processor has an internal cache, and wherein the method further comprises tracking a ratio of bus cycles to bus cycles during memory accesses.
Claim 11
Dependent Claim
70 words
The method of claim 5 wherein the system has a plurality of levels of cache and wherein the method further comprises the steps of: tracking a ratio of bus cycles to bus cycles during which a particular level of cache is accessed; tracking a ratio of cache hits to cache misses for the particular cache level; and setting the mode of the particular cache level operation based on the ratios.
Claim 12
Dependent Claim
23 words
The method of claim 5 wherein only a bank of the data cache containing the information is enabled responsive to a cache hit.
Claim 13
Dependent Claim
104 words
In a computer system having a CPU coupled to a memory by a bus, an apparatus for optimizing characteristics of a memory subsystem comprising: means for recording behavior of the subsystem; and means for dynamically enabling portions of the memory subsystem in response to the recorded behavior wherein a tag cache is enabled if the recorded behavior indicates a first probability of an event, a data cache is enabled if the recorded behavior indicates a second probability of the event and the data cache is only enabled if the event occurs if the recorded behavior does not indicate the second probability of the event.
Claim 14
Dependent Claim
104 words
In a computer system having a CPU coupled to a memory by a bus, an apparatus for optimizing characteristics of a memory subsystem comprising: means for recording behavior of the subsystem; and means for dynamically enabling portions of the memory subsystem in response to the recorded behavior wherein a tag cache is enabled if the recorded behavior indicates a first probability of an event, a data cache is enabled if the recorded behavior indicates a second probability of the event and the data cache is only enabled if the event occurs if the recorded behavior does not indicate the second probability of the event.
Claim 15
Dependent Claim
32 words
The apparatus of claim 10 wherein the means for recording comprises: means for tracking the ratio of bus cycles to bus cycles during which a portion of the memory subsystem is accessed.
Claim 16
Dependent Claim
43 words
The apparatus of claim 10 wherein the means for recording comprises first means for predicting a probability of a cache hit; and wherein the means for dynamically enabling comprises means for dynamically setting a mode of cache operation responsive to the predicting means.
Claim 17
Dependent Claim
49 words
The apparatus of claim 12 wherein the means for dynamically enabling further comprises: second means for predicting a probability of a page hit in main memory; and means for dynamically setting a mode of main memory operation responsive to the predicting means, second predicting means, and the tracking means.
Claim 18
Dependent Claim
18 words
The apparatus of claim 13 wherein the first and second predicting means comprise up-down counters coupled to comparators.
Claim 19
Dependent Claim
27 words
The apparatus of claim 12 wherein the dynamically setting means further comprises first means for enabling the tag cache; and second means for enabling the data cache.
Claim 20
Dependent Claim
20 words
The apparatus of claim 15 wherein the second enabling means can independently enable individual data arrays within the data cache.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-11 | 2002-07-13 | 2003-01-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-11 | 2006-07-13 | 2007-01-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-11 | 2010-07-13 | 2011-01-12 | $7700.00 | Window Closed / Lapsed |